Spectrum Brands C6x VME64 manual Performance and Data Throughput, Data Access/Transfer Performance

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Spectrum Signal Processing

Monaco Technical Reference

 

Specifications

10.3. Performance and Data Throughput

The following table gives the data transfer rates between different memory, processor and interface resources on the Monaco board. Monaco boards using the TMS320C6201 processor have a clock speed of 200 MHz; Monaco67 boards using the TMS230C6701 processor have a clock speed of 167 MHz.

Table 15 Data Access/Transfer Performance

 

 

Clock Speed

Units

 

 

 

 

 

 

 

Source

Target

200

167

MHz

Comment

 

 

 

 

 

 

‘C6x

Local SBSRAM

400

333

MB/s

 

 

 

 

 

 

 

 

Local SDRAM

400

333

MB/s

 

 

 

 

 

 

 

 

PEM Site

400

333

MB/s

 

 

 

 

 

 

 

 

Global SRAM read

88

74

MB/s

 

 

 

 

 

 

 

 

Global SRAM write

100

83

MB/s

 

 

 

 

 

 

 

 

DSP~LINK3 Standard

15

12.5

MB/s

 

 

 

 

 

 

 

 

DSP~LINK3 Standard Fast

28

24

MB/s

 

 

 

 

 

 

 

 

Hurricane Registers

115

138

ns

 

 

 

 

 

 

 

 

VMEbus (master) read

 

2

MB/s

Coupled read. Typical value for a "real" slave, which is slower

 

 

 

 

 

than for an "ideal" VME slave.

 

 

 

 

 

 

 

VMEbus (master) write

 

9

MB/s

De-coupled write. Typical value for a "real" slave, which is

 

 

 

 

 

slower than for an "ideal" VME slave.

 

 

 

 

 

 

VME Host

Global SRAM

 

40

MB/s

 

 

 

 

 

 

 

 

Hurricane Registers

 

150

ns

 

 

 

 

 

 

 

 

HPI read

 

14

MB/s

Maximum speed from internal ‘C6x memory when the ‘C6x is

 

 

 

 

 

not accessing memory

 

 

 

 

 

 

 

HPI write

 

28

MB/s

Maximum speed to internal ‘C6x memory when the ‘C6x is not

 

 

 

 

 

accessing memory.

 

 

 

 

 

 

SCV64 DMA

Global SRAM

 

40

MB/s

 

 

 

 

 

 

 

 

Hurricane Registers

 

150

ns

 

 

 

 

 

 

 

 

VMEbus (master) read

 

80

MB/s

 

 

 

 

 

 

 

 

VMEbus (master) write

 

80

MB/s

 

 

 

 

 

 

 

Hurricane DMA

Global SRAM R/W

 

128

MB/s

 

 

 

 

 

 

 

PMC Site

Global SRAM R/W

 

128

MB/s

 

 

 

 

 

 

 

Part Number 500-00191

61

Revision 2.00

 

Image 73
Contents Monaco Revision Iii PrefaceChange Document Rev Date ChangesHistory Table of Contents Monaco Technical Reference Vii Viii List of Figures Table of Contents List of Tables Xii Introduction FeaturesProduct Operation Processors VME InterfacesPMC PEMReference Documents General Bus Architecture On-Board Power SupplyVME A24 Slave Interface Reset Reset ConditionsJtag Reset SysresetBoard Layout Board LayoutJumper Settings Description Jumper settingsOUT Part Number Processor Nodes Processor Configurations PopulatedProcessor Node Block Diagram Internal Memory Processor Memory ConfigurationExternal Memory 0x0180 DSP Memory Map Nodes B, C, and D AddressSynchronous Dram Synchronous Burst SramProcessor Expansion Module Host PortProcessor Boot Source Jumpers Node Processor BootingSerial Port Routing Serial Port RoutingVME and PMC Connections for Serial Port PEM Connections for Serial Port 0Global Shared Bus Global Shared Bus Access Source TargetMemory ArbitrationBurst Cycle Bus Access Single Cycle Bus AccessLocked Cycles Global Shared Bus VME Operation VME64 Bus InterfaceSCV64 Primary Slave A32/A24 Interface A24 Secondary Slave Interface AccessA24 Secondary Interface Memory Map Hpia HPI Register Addresses VME addressMaster A32/A24/A16 SCV64 Interface VME64 Bus Interface DSP~LINK3 Data Transfer Operating Modes DSP~LINK3 InterfaceAstrben Address Strobe Control ModeDSP~LINK3 Reset Interface SignalsDSP~LINK3 Interface PCI Interface Hurricane ConfigurationPCI Offset Address Value Initialize Hurricane Register SetBCC2A PCI Device Hurricane ImplementationJtag Chain Jtag DebuggingJtag Debugging Overview Interrupt HandlingInterrupt Routing DSP~LINK3 Interrupts to Node aPCI Bus Interrupts PEM InterruptsHurricane Interrupt SCV64 InterruptKIPL2 KIPL1 KIPL0 Kipl Status Bits and the Iack CycleBit Node Whose Access Caused the Bus Error Bus Error InterruptsVME Host Interrupts To Any Node Inter-processor InterruptsRegisters Register Address Summary Access Privilege BusKFC2..0 KSIZE1..0 KADDR1..0 Vpage RegisterVstatus Register Kavec BuserraKIPL2..0 Vinta Register Vintb Register Vintc Register Vintd Register Kiplend Kipl Enable RegisterKiplenc KiplenbDSP~LINK3 Register DL3RESETID Register Hinta VME A24 Status RegisterHintb HintcVME A24 Control Register Registers Board Identification SpecificationsMonaco Monaco67General Specifications ParameterPerformance and Data Throughput Data Access/Transfer PerformanceSpecifications Connector Layout Connector PinoutsVME P1 Connector Pinout VME ConnectorsVME P2 Connector Pinout PMC to VME P2 VME P2 Connector DSP~LINK3 to VME P2 PMC Connector JN1 Pinout PMC ConnectorsPMC Connector JN2 PMC Connector JN4 Non-standard PMC Connector JN5 PEM 1 Connector Pinout PEM ConnectorsPEM 2 Connector Pinout Jtag in Connector Pinout Jtag ConnectorsJtag OUT Connector Connector Pinouts SCV64 Register Initialization Appendix a SCV64 Register ValuesSCV64 Register Initialization VME IndexInterrupts to node A, 40 register Reset Jtag Sysreset