Spectrum Brands C6x VME64 manual List of Figures

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Spectrum Signal Processing	Monaco Technical Reference
	Table of Contents

List of Figures

Figure 1 Block Diagram		4
Figure 2	Board Layout	6
Figure 3	Processor Node Block Diagram	10
Figure 4	DSP Memory Map	13
Figure 5	DSP Memory Map for External-Memory Space CE1	14
Figure 6	Serial Port Routing	17
Figure 7	Global Bus Arbitration	20
Figure 8	Primary VME A24/A32 Memory Map	24
Figure 9	A24 Secondary Interface Memory Map	25
Figure 10	PCI Memory Map	33
Figure 11	JTAG Chain	37
Figure 12	Interrupt Routing	40
Figure 13	Connector Layout	63

Part Number 500-00191	ix
Revision 2.00

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Contents Monaco Revision Iii PrefaceDocument Rev Date Changes ChangeHistory Table of Contents Monaco Technical Reference Vii Viii List of Figures Table of Contents List of Tables Xii Features IntroductionProduct Operation Processors VME InterfacesPMC PEMReference Documents General Bus Architecture On-Board Power SupplyVME A24 Slave Interface Reset Reset ConditionsJtag Reset SysresetBoard Layout Board LayoutJumper settings Jumper Settings DescriptionOUT Part Number Processor Nodes Processor Configurations PopulatedProcessor Node Block Diagram Processor Memory Configuration Internal MemoryExternal Memory 0x0180 DSP Memory Map Nodes B, C, and D AddressSynchronous Dram Synchronous Burst SramProcessor Expansion Module Host PortProcessor Boot Source Jumpers Node Processor BootingSerial Port Routing Serial Port RoutingVME and PMC Connections for Serial Port PEM Connections for Serial Port 0Global Shared Bus Global Shared Bus Access Source TargetMemory ArbitrationBurst Cycle Bus Access Single Cycle Bus AccessLocked Cycles Global Shared Bus VME64 Bus Interface VME OperationSCV64 Primary Slave A32/A24 Interface A24 Secondary Slave Interface AccessA24 Secondary Interface Memory Map Hpia HPI Register Addresses VME addressMaster A32/A24/A16 SCV64 Interface VME64 Bus Interface DSP~LINK3 Data Transfer Operating Modes DSP~LINK3 InterfaceAstrben Address Strobe Control ModeDSP~LINK3 Reset Interface SignalsDSP~LINK3 Interface Hurricane Configuration PCI InterfacePCI Offset Address Value Initialize Hurricane Register SetBCC2A PCI Device Hurricane ImplementationJtag Chain Jtag DebuggingJtag Debugging Overview Interrupt HandlingInterrupt Routing DSP~LINK3 Interrupts to Node aPCI Bus Interrupts PEM InterruptsHurricane Interrupt SCV64 InterruptKIPL2 KIPL1 KIPL0 Kipl Status Bits and the Iack CycleBit Node Whose Access Caused the Bus Error Bus Error InterruptsVME Host Interrupts To Any Node Inter-processor InterruptsRegisters Register Address Summary Access Privilege BusKFC2..0 KSIZE1..0 KADDR1..0 Vpage RegisterVstatus Register Buserra KavecKIPL2..0 Vinta Register Vintb Register Vintc Register Vintd Register Kiplend Kipl Enable RegisterKiplenc KiplenbDSP~LINK3 Register DL3RESETID Register Hinta VME A24 Status RegisterHintb HintcVME A24 Control Register Registers Board Identification SpecificationsMonaco Monaco67General Specifications ParameterPerformance and Data Throughput Data Access/Transfer PerformanceSpecifications Connector Layout Connector PinoutsVME P1 Connector Pinout VME ConnectorsVME P2 Connector Pinout PMC to VME P2 VME P2 Connector DSP~LINK3 to VME P2 PMC Connector JN1 Pinout PMC ConnectorsPMC Connector JN2 PMC Connector JN4 Non-standard PMC Connector JN5 PEM 1 Connector Pinout PEM ConnectorsPEM 2 Connector Pinout Jtag Connectors Jtag in Connector PinoutJtag OUT Connector Connector Pinouts SCV64 Register Initialization Appendix a SCV64 Register ValuesSCV64 Register Initialization VME IndexInterrupts to node A, 40 register Reset Jtag Sysreset