Spectrum Brands C6x VME64 manual DSP~LINK3 Interrupts to Node a, Interrupt Routing

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Monaco Technical Reference

Spectrum Signal Processing

Interrupt Handling

KIPL D Enable

SCV64 Interrupt

VME Interrupt

BUSERR_D

INT 4

VINTD

PCI Interrupt

INT 5

Node D

'C6x

PEM INT1

INT 6

PEM INT2

Hurricane

INT 7

KIPL C Enable

VME Interrupt

INT 4

BUSERR_C

VINTC

PCI Interrupt

INT 5

Node C

'C6x

PEM INT1

INT 6

PEM INT2

Hurricane

INT 7

KIPL B Enable

VME Interrupt

INT 4

BUSERR_B

VINTB

PCI Interrupt

INT 5

Node B

'C6x

PEM INT1

INT 6

PEM INT2

Hurricane

INT 7

KIPL A Enable

VME Interrupt

BUSERR_A

INT 4

PCI Interrupt

VINTA

INT 5

Node A

Hurricane

Hurricane

'C6x

PEM INT1

INT 6

PCI Bus

INTA

De-Bounce Logic

PEM INT2

INTB

INT 7

Interrupts

INTC

INTD

DSP~LINK3

INT0

Note

INT1

‘C6x interrupts

Interface

De-Bounce Logic

are rising edge-

INT2

Interrupts

triggered.

INT3

Figure 12 Interrupt Routing

8.2.DSP~LINK3 Interrupts to Node A

The four active-low interrupts from the DSP~LINK3 interface are logically OR’ed and routed to the INT7 interrupt input of the node A ‘C6x. The open-collector signals are de- bounced. The interrupts are not latched on the Monaco board and must be cleared on the DSP~LINK3 board that generated them.

40	Part Number 500-00191
	Revision 2.00

Image 52

Contents Monaco Revision Preface IiiChange Document Rev Date ChangesHistory Table of Contents Monaco Technical Reference Vii Viii List of Figures Table of Contents List of Tables Xii Introduction FeaturesProduct Operation Processors Interfaces VMEPMC PEMReference Documents On-Board Power Supply General Bus ArchitectureReset Conditions VME A24 Slave Interface ResetJtag Reset SysresetBoard Layout Board LayoutJumper Settings Description Jumper settingsOUT Part Number Processor Configurations Populated Processor NodesProcessor Node Block Diagram Internal Memory Processor Memory ConfigurationExternal Memory 0x0180 DSP Memory Map Address Nodes B, C, and DSynchronous Burst Sram Synchronous DramProcessor Expansion Module Host PortProcessor Booting Processor Boot Source Jumpers NodeSerial Port Routing Serial Port RoutingPEM Connections for Serial Port 0 VME and PMC Connections for Serial PortGlobal Shared Bus Access Source Target Global Shared BusMemory ArbitrationSingle Cycle Bus Access Burst Cycle Bus AccessLocked Cycles Global Shared Bus VME Operation VME64 Bus InterfaceSCV64 Primary Slave A32/A24 Interface Access A24 Secondary Slave InterfaceA24 Secondary Interface Memory Map HPI Register Addresses VME address HpiaMaster A32/A24/A16 SCV64 Interface VME64 Bus Interface DSP~LINK3 Interface DSP~LINK3 Data Transfer Operating ModesAddress Strobe Control Mode AstrbenInterface Signals DSP~LINK3 ResetDSP~LINK3 Interface PCI Interface Hurricane ConfigurationPCI Offset Address Hurricane Register Set Value InitializeBCC2A Hurricane Implementation PCI DeviceJtag Debugging Jtag ChainJtag Debugging Interrupt Handling OverviewDSP~LINK3 Interrupts to Node a Interrupt RoutingPEM Interrupts PCI Bus InterruptsHurricane Interrupt SCV64 InterruptKipl Status Bits and the Iack Cycle KIPL2 KIPL1 KIPL0Bus Error Interrupts Bit Node Whose Access Caused the Bus ErrorInter-processor Interrupts VME Host Interrupts To Any NodeRegister Address Summary Access Privilege Bus RegistersVpage Register KFC2..0 KSIZE1..0 KADDR1..0Vstatus Register Kavec BuserraKIPL2..0 Vinta Register Vintb Register Vintc Register Vintd Register Kipl Enable Register KiplendKiplenc KiplenbDL3RESET DSP~LINK3 RegisterID Register VME A24 Status Register HintaHintb HintcVME A24 Control Register Registers Specifications Board IdentificationMonaco Monaco67Specifications Parameter GeneralData Access/Transfer Performance Performance and Data ThroughputSpecifications Connector Pinouts Connector LayoutVME Connectors VME P1 Connector PinoutVME P2 Connector Pinout PMC to VME P2 VME P2 Connector DSP~LINK3 to VME P2 PMC Connectors PMC Connector JN1 PinoutPMC Connector JN2 PMC Connector JN4 Non-standard PMC Connector JN5 PEM Connectors PEM 1 Connector PinoutPEM 2 Connector Pinout Jtag in Connector Pinout Jtag ConnectorsJtag OUT Connector Connector Pinouts Appendix a SCV64 Register Values SCV64 Register InitializationSCV64 Register Initialization Index VMEInterrupts to node A, 40 register Reset Jtag Sysreset