Spectrum Brands C6x VME64 manual DSP~LINK3 Interface, DSP~LINK3 Data Transfer Operating Modes

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Spectrum Signal Processing	Monaco Technical Reference
	DSP~LINK3 Interface

5 DSP~LINK3 Interface

The Monaco board provides a DSP~LINK3 interface through a ribbon cable connector. The interface supports up to 4 slave DSP~LINK3 devices. The ribbon cable can be up to 12 inches (30 cm) long.

The DSP~LINK3 interface is accessed from node A’s local bus only; it is not accessible from any other node nor from the VME bus. Accesses to the DSP~LINK3 interface do not require the Global Shared Bus. As a result, DSP~LINK3 accesses can happen concurrently with Global Shared Bus access by other devices (such as the other processors or the SCV64 chip).

If a DSP~LINK3 access is interleaved within global shared SRAM accesses, node A acquires the Global Shared Bus, performs the SRAM access, releases the Global Shared Bus, performs the DSP~LINK3 access, acquires the Global Shared Bus, and then performs the next Global Shared Bus SRAM access using a control register.

5.1.DSP~LINK3 Data Transfer Operating Modes

The Monaco board supports four data transfer operating modes.

∙Standard Access

∙Standard Fast Access

∙Address Strobe Control

∙Ready Control Access

The three “access” data transfer operating modes (Standard, Standard Fast and Ready Control) of the DSP~LINK3 interface use three 64K address spaces accessed from node A. Each of the three “access” modes is assigned its own 64K memory space. Address Strobe Control cycles are multiplexed with the Standard Fast Access mode space.

The following table shows how the DSP~LINK3 data transfer operating modes are supported.

Part Number 500-00191	29
Revision 2.00

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Contents Monaco Revision Iii PrefaceHistory Document Rev Date ChangesChange Table of Contents Monaco Technical Reference Vii Viii List of Figures Table of Contents List of Tables Xii Product Operation Processors FeaturesIntroduction VME InterfacesPMC PEMReference Documents General Bus Architecture On-Board Power SupplyVME A24 Slave Interface Reset Reset ConditionsJtag Reset SysresetBoard Layout Board LayoutOUT Jumper settingsJumper Settings Description Part Number Processor Nodes Processor Configurations PopulatedProcessor Node Block Diagram External Memory Processor Memory ConfigurationInternal Memory 0x0180 DSP Memory Map Nodes B, C, and D AddressSynchronous Dram Synchronous Burst SramProcessor Expansion Module Host PortProcessor Boot Source Jumpers Node Processor BootingSerial Port Routing Serial Port RoutingVME and PMC Connections for Serial Port PEM Connections for Serial Port 0Global Shared Bus Global Shared Bus Access Source TargetMemory ArbitrationBurst Cycle Bus Access Single Cycle Bus AccessLocked Cycles Global Shared Bus SCV64 Primary Slave A32/A24 Interface VME64 Bus InterfaceVME Operation A24 Secondary Slave Interface AccessA24 Secondary Interface Memory Map Hpia HPI Register Addresses VME addressMaster A32/A24/A16 SCV64 Interface VME64 Bus Interface DSP~LINK3 Data Transfer Operating Modes DSP~LINK3 InterfaceAstrben Address Strobe Control ModeDSP~LINK3 Reset Interface SignalsDSP~LINK3 Interface PCI Offset Address Hurricane ConfigurationPCI Interface Value Initialize Hurricane Register SetBCC2A PCI Device Hurricane ImplementationJtag Chain Jtag DebuggingJtag Debugging Overview Interrupt HandlingInterrupt Routing DSP~LINK3 Interrupts to Node aPCI Bus Interrupts PEM InterruptsHurricane Interrupt SCV64 InterruptKIPL2 KIPL1 KIPL0 Kipl Status Bits and the Iack CycleBit Node Whose Access Caused the Bus Error Bus Error InterruptsVME Host Interrupts To Any Node Inter-processor InterruptsRegisters Register Address Summary Access Privilege BusKFC2..0 KSIZE1..0 KADDR1..0 Vpage RegisterVstatus Register KIPL2..0 BuserraKavec Vinta Register Vintb Register Vintc Register Vintd Register Kiplend Kipl Enable RegisterKiplenc KiplenbDSP~LINK3 Register DL3RESETID Register Hinta VME A24 Status RegisterHintb HintcVME A24 Control Register Registers Board Identification SpecificationsMonaco Monaco67General Specifications ParameterPerformance and Data Throughput Data Access/Transfer PerformanceSpecifications Connector Layout Connector PinoutsVME P1 Connector Pinout VME ConnectorsVME P2 Connector Pinout PMC to VME P2 VME P2 Connector DSP~LINK3 to VME P2 PMC Connector JN1 Pinout PMC ConnectorsPMC Connector JN2 PMC Connector JN4 Non-standard PMC Connector JN5 PEM 1 Connector Pinout PEM ConnectorsPEM 2 Connector Pinout Jtag OUT Connector Jtag ConnectorsJtag in Connector Pinout Connector Pinouts SCV64 Register Initialization Appendix a SCV64 Register ValuesSCV64 Register Initialization VME IndexInterrupts to node A, 40 register Reset Jtag Sysreset