Spectrum Brands C6x VME64 manual Jtag Debugging, Jtag Chain

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Spectrum Signal Processing	Monaco Technical Reference
	JTAG Debugging

7 JTAG Debugging

The Monaco board supports JTAG in-circuit emulation from a built in 74ACT8990 Test Bus Controller. The 74ACT8990 Test Bus Controller permits the VME interface to operate the JTAG chain. There are also two JTAG connectors for an XDS510 or White Mountain debugger, JTAG IN (J1) and JTAG OUT (J2), which can route the JTAG chain off-board.

JTAG in-circuit emulation is fed to the Test Bus Controller from the VME A24 secondary interface. C source debugging using an emulator board running a debug monitor on an adjacent computer is supported through the JTAG IN connector. If a JTAG IN connection with a clock signal is present the Test Bus Controller is automatically disconnected.

JTAG data lines are routed to each available ‘C6x node. The full JTAG chain is shown in the following diagram. Unpopulated processor nodes are bypassed.

TDO

TDO JTAG OUT

TDI

Routed back to JTAG IN if nothing is connected to

JTAG OUT

The Test Bus Controller		TDO
(TBC) is disabled		TDO
(TBC) is disabled
(bypassed) if an external				TDI
(bypassed) if an external		JTAG IN or TBC		TDI
debugger is connected to		JTAG IN or TBC
the JTAG IN connector.
the JTAG IN connector.

Node D ‘C6x

TDI

TDO

Node C ‘C6x

TDI

TDO

Node B ‘C6x

TDI

TDO

Node A ‘C6x

Figure 11 JTAG Chain

The JTAG IN input is buffered to reduce the load on an external JTAG device. The JTAG OUT output is buffered to guarantee enough drive to external JTAG loads. Up to three Monaco boards can be chained together through JTAG.

Part Number 500-00191	37
Revision 2.00

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Contents Monaco Revision Iii PrefaceChange Document Rev Date ChangesHistory Table of Contents Monaco Technical Reference Vii Viii List of Figures Table of Contents List of Tables Xii Introduction FeaturesProduct Operation Processors VME InterfacesPMC PEMReference Documents General Bus Architecture On-Board Power SupplyVME A24 Slave Interface Reset Reset ConditionsJtag Reset SysresetBoard Layout Board LayoutJumper Settings Description Jumper settingsOUT Part Number Processor Nodes Processor Configurations PopulatedProcessor Node Block Diagram Internal Memory Processor Memory ConfigurationExternal Memory 0x0180 DSP Memory Map Nodes B, C, and D AddressSynchronous Dram Synchronous Burst SramProcessor Expansion Module Host PortProcessor Boot Source Jumpers Node Processor BootingSerial Port Routing Serial Port RoutingVME and PMC Connections for Serial Port PEM Connections for Serial Port 0Global Shared Bus Global Shared Bus Access Source TargetMemory ArbitrationBurst Cycle Bus Access Single Cycle Bus AccessLocked Cycles Global Shared Bus VME Operation VME64 Bus InterfaceSCV64 Primary Slave A32/A24 Interface A24 Secondary Slave Interface AccessA24 Secondary Interface Memory Map Hpia HPI Register Addresses VME addressMaster A32/A24/A16 SCV64 Interface VME64 Bus Interface DSP~LINK3 Data Transfer Operating Modes DSP~LINK3 InterfaceAstrben Address Strobe Control ModeDSP~LINK3 Reset Interface SignalsDSP~LINK3 Interface PCI Interface Hurricane ConfigurationPCI Offset Address Value Initialize Hurricane Register SetBCC2A PCI Device Hurricane ImplementationJtag Chain Jtag DebuggingJtag Debugging Overview Interrupt HandlingInterrupt Routing DSP~LINK3 Interrupts to Node aPCI Bus Interrupts PEM InterruptsHurricane Interrupt SCV64 InterruptKIPL2 KIPL1 KIPL0 Kipl Status Bits and the Iack CycleBit Node Whose Access Caused the Bus Error Bus Error InterruptsVME Host Interrupts To Any Node Inter-processor InterruptsRegisters Register Address Summary Access Privilege BusKFC2..0 KSIZE1..0 KADDR1..0 Vpage RegisterVstatus Register Kavec BuserraKIPL2..0 Vinta Register Vintb Register Vintc Register Vintd Register Kiplend Kipl Enable RegisterKiplenc KiplenbDSP~LINK3 Register DL3RESETID Register Hinta VME A24 Status RegisterHintb HintcVME A24 Control Register Registers Board Identification SpecificationsMonaco Monaco67General Specifications ParameterPerformance and Data Throughput Data Access/Transfer PerformanceSpecifications Connector Layout Connector PinoutsVME P1 Connector Pinout VME ConnectorsVME P2 Connector Pinout PMC to VME P2 VME P2 Connector DSP~LINK3 to VME P2 PMC Connector JN1 Pinout PMC ConnectorsPMC Connector JN2 PMC Connector JN4 Non-standard PMC Connector JN5 PEM 1 Connector Pinout PEM ConnectorsPEM 2 Connector Pinout Jtag in Connector Pinout Jtag ConnectorsJtag OUT Connector Connector Pinouts SCV64 Register Initialization Appendix a SCV64 Register ValuesSCV64 Register Initialization VME IndexInterrupts to node A, 40 register Reset Jtag Sysreset