Spectrum Brands C6x VME64 manual VME64 Bus Interface, VME Operation

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Spectrum Signal Processing	Monaco Technical Reference
	VME64 Bus Interface

4 VME64 Bus Interface

There are two separate VMEbus slave interfaces on the Monaco board. One is implemented by the SCV64 and provides A32 and A24 VMEbus masters access to the global shared bus. The second slave interface provides direct access to the Test Bus Controller for debugging, and to the Host Port Interfaces (HPIs) of each ‘C6x. The HPI provides support for code download, control, and data transfers from the VME64 bus.

4.1.VME Operation

The Monaco board requires a VME chassis (6U) with power supply. The board automatically becomes VMEbus system controller (Syscon) if it resides at the top of the VMEbus grant daisy chain. This capability is provided by the Tundra SCV64 interface chip. Refer to the SCV64 User Manual for details.

The Monaco board has two VME backplane connectors: a 3 row P1 connector and a 5 row P2 connector.

The board may be installed in either a 5 row VME backplane or a 3 row backplane. The two additional rows on the VME P2 connector (Z and D) only serve to route serial port signals from DSP processor nodes A, B, C and D to the VME backplane, if the board is configured for that option.

Note: If the Monaco board is installed in a 3 row VME chassis, serial port routing will be restricted to the PEM and PMC sites only.

4.2.SCV64 Primary Slave A32/A24 Interface

The primary interface to the VME64 bus is based on Tundra Semiconductor Corporation’s SCV64 VME64 Interface chip. This chip enables the Monaco board to act as a master or a slave on the VME64 bus, and also provides VME interrupt capabilities. Transfer rates of 40 MBytes/sec are supported between the SCV64 and the Global Shared Bus SRAM once the bus has been acquired. The SCV64 cannot be pre-empted from the Global Shared Bus and it does not have a bus ownership timer.

A host on the VME64 bus can access both the lower half (1 Mbyte) of Global SRAM and the Hurricane control registers on a Monaco board in either A24 or A32 addressing modes as shown in the following memory map.

Part Number 500-00191	23
Revision 2.00

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Contents Monaco Revision Iii PrefaceHistory Document Rev Date ChangesChange Table of Contents Monaco Technical Reference Vii Viii List of Figures Table of Contents List of Tables Xii Product Operation Processors FeaturesIntroduction PEM InterfacesVME PMCReference Documents General Bus Architecture On-Board Power SupplySysreset Reset ConditionsVME A24 Slave Interface Reset Jtag ResetBoard Layout Board LayoutOUT Jumper settingsJumper Settings Description Part Number Processor Nodes Processor Configurations PopulatedProcessor Node Block Diagram External Memory Processor Memory ConfigurationInternal Memory 0x0180 DSP Memory Map Nodes B, C, and D AddressHost Port Synchronous Burst SramSynchronous Dram Processor Expansion ModuleProcessor Boot Source Jumpers Node Processor BootingSerial Port Routing Serial Port RoutingVME and PMC Connections for Serial Port PEM Connections for Serial Port 0Arbitration Global Shared Bus Access Source TargetGlobal Shared Bus MemoryBurst Cycle Bus Access Single Cycle Bus AccessLocked Cycles Global Shared Bus SCV64 Primary Slave A32/A24 Interface VME64 Bus InterfaceVME Operation A24 Secondary Slave Interface AccessA24 Secondary Interface Memory Map Hpia HPI Register Addresses VME addressMaster A32/A24/A16 SCV64 Interface VME64 Bus Interface DSP~LINK3 Data Transfer Operating Modes DSP~LINK3 InterfaceAstrben Address Strobe Control ModeDSP~LINK3 Reset Interface SignalsDSP~LINK3 Interface PCI Offset Address Hurricane ConfigurationPCI Interface Value Initialize Hurricane Register SetBCC2A PCI Device Hurricane ImplementationJtag Chain Jtag DebuggingJtag Debugging Overview Interrupt HandlingInterrupt Routing DSP~LINK3 Interrupts to Node aSCV64 Interrupt PEM InterruptsPCI Bus Interrupts Hurricane InterruptKIPL2 KIPL1 KIPL0 Kipl Status Bits and the Iack CycleBit Node Whose Access Caused the Bus Error Bus Error InterruptsVME Host Interrupts To Any Node Inter-processor InterruptsRegisters Register Address Summary Access Privilege BusKFC2..0 KSIZE1..0 KADDR1..0 Vpage RegisterVstatus Register KIPL2..0 BuserraKavec Vinta Register Vintb Register Vintc Register Vintd Register Kiplenb Kipl Enable RegisterKiplend KiplencDSP~LINK3 Register DL3RESETID Register Hintc VME A24 Status RegisterHinta HintbVME A24 Control Register Registers Monaco67 SpecificationsBoard Identification MonacoGeneral Specifications ParameterPerformance and Data Throughput Data Access/Transfer PerformanceSpecifications Connector Layout Connector PinoutsVME P1 Connector Pinout VME ConnectorsVME P2 Connector Pinout PMC to VME P2 VME P2 Connector DSP~LINK3 to VME P2 PMC Connector JN1 Pinout PMC ConnectorsPMC Connector JN2 PMC Connector JN4 Non-standard PMC Connector JN5 PEM 1 Connector Pinout PEM ConnectorsPEM 2 Connector Pinout Jtag OUT Connector Jtag ConnectorsJtag in Connector Pinout Connector Pinouts SCV64 Register Initialization Appendix a SCV64 Register ValuesSCV64 Register Initialization VME IndexInterrupts to node A, 40 register Reset Jtag Sysreset