Spectrum Brands C6x VME64 manual BCC2A

Page 47

Spectrum Signal Processing	Monaco Technical Reference
	PCI Interface

Hurricane DSP Offset

'C6x	PCI Bus	Slave A32/A24	Register Description
Address	Offset	SCV64 Offset

Value Initialize

0x28	0x016C 00A0	0x0020 00A0	0x0020 00A0	BCC2A	DSP Cycle control 2A	0x0000 0000
0x29	0x016C 00A4	0x0020 00A4	0x0020 00A4	BCC2B	DSP Cycle control 2B	0x0000 0000
0x2A	0x016C 00A8	0x0020 00A8	0x0020 00A8	BCC2C	DSP Cycle control 2C	0x0000 0000
0x2B	0x016C 00AC	0x0020 00AC	0x0020 00AC	BCC2D	DSP Cycle control 2D	0x0000 0000
0x2C	0x016C 00B0	0x0020 00B0	0x0020 00B0	BCC3A	DSP Cycle control 3A	0x00D6 1DE0
0x2D	0x016C 00B4	0x0020 00B4	0x0020 00B4	BCC3B	DSP Cycle control 3B	0x0000 0000
0x2E	0x016C 00B8	0x0020 00B8	0x0020 00B8	BCC3C	DSP Cycle control 3C	0xA9E0 69A0
0x2F	0x016C 00BC	0x0020 00BC	0x0020 00BC	BCC3D	DSP Cycle control 3D	0x0000 0000
0x30	0x016C 00C0	0x0020 00C0	0x0020 00C0	BMI0	Bank 0 Mapping Information	0x1000 0003	Y
0x31	0x016C 00C4	0x0020 00C4	0x0020 00C4	BMI1	Bank 1 Mapping Information	0x0000 0000
0x32	0x016C 00C8	0x0020 00C8	0x0020 00C8	BMI2	Bank 2 Mapping Information	0x0000 0000
0x33	0x016C 00CC	0x0020 00CC	0x0020 00CC	BMI3	Bank 3 Mapping Information	0x0000 0000
0x34	0x016C 00D0	0x0020 00D0	0x0020 00D0	BMI4	Bank 4 Mapping Information	0x0000 0000
0x35	0x016C 00D4	0x0020 00D4	0x0020 00D4	BMI5	Bank 5 Mapping Information	0x0000 0000
0x36	0x016C 00D8	0x0020 00D8	0x0020 00D8	BMI6	Bank 6 Mapping Information	0x0000 0000
0x37	0x016C 00DC	0x0020 00DC	0x0020 00DC	BMI7	Bank 7 Mapping Information	0x0000 0000
0x38	0x016C 00E0	0x0020 00E0	0x0020 00E0	BMI8	Bank 8 Mapping Information	0x0000 0000
0x39	0x016C 00E4	0x0020 00E4	0x0020 00E4	CSCR	Cycle select (all banks)	0x0000 0000	Y

0x3A

0x016C 00E8

0x0020 00E8

0x0020 00E8

MABE	Map Bank Enable
CSER	Chip Select Enable
BER	Mask Broadcast

0x0001 0100

Y

0x3B	0x016C 00EC	0x0020 00EC	0x0020 00EC	IRBAR	Internal Register Base Address Register	0x0020 0000	Y
0x3C	0x016C 00F0	0x0020 00F0	0x0020 00F0	PCS	Programmable Chip Select	0x0000 0000	Y
0x3D	0x016C 00F4	0x0020 00F4	0x0020 00F4	DSPBT	DSP bus timer control register	0x0000 0000
0x3E	0x016C 00F8	0x0020 00F8	0x0020 00F8	DBIC	DSP bus interface control	0x0000 0000
0x3F	0x016C 00FC	0x0020 00FC	0x0020 00FC		reserved	0x0000 0000

	0x40	0x016C 0100	0x0020 0100	0x0020 0100
	0x41	0x016C 0104	0x0020 0104	0x0020 0104
	0x42	0x016C 0108	0x0020 0108	0x0020 0108
	0x43	0x016C 010C	0x0020 010C	0x0020 010C
	0x44	0x016C 0110	0x0020 0110	0x0020 0110
	0x45	0x016C 0114	0x0020 0114	0x0020 0114
	0x46	0x016C 0118	0x0020 0118	0x0020 0118
	0x47	0x016C 011C	0x0020 011C	0x0020 011C
	0x48	0x016C 0120	0x0020 0120	0x0020 0120
	0x49	0x016C 0124	0x0020 0124	0x0020 0124
	0x4A	0x016C 0128	0x0020 0128	0x0020 0128
	0x4B	0x016C 012C	0x0020 012C	0x0020 012C
	0x4C	0x016C 0130	0x0020 0130	0x0020 0130
	0x4D	0x016C 0134	0x0020 0134	0x0020 0134
	0x4E	0x016C 0138	0x0020 0138	0x0020 0138

PCI Configuration Registers

0xFFFF12FB

0x0280 0006

0x0680 0000

0x0000 0000

0x0000 0000

0x0000 0000

0x0000 0000

0x0000 0000

0x0000 0000

0x0000 0000

0x0000 0000

0xFFFF FFFF

0x0000 0000

0x0000 0000

0x0000 0000

Part Number 500-00191	35
Revision 2.00

Image 47

Contents Monaco Revision Iii PrefaceHistory Document Rev Date ChangesChange Table of Contents Monaco Technical Reference Vii Viii List of Figures Table of Contents List of Tables Xii Product Operation Processors FeaturesIntroduction PEM InterfacesVME PMCReference Documents General Bus Architecture On-Board Power SupplySysreset Reset ConditionsVME A24 Slave Interface Reset Jtag ResetBoard Layout Board LayoutOUT Jumper settingsJumper Settings Description Part Number Processor Nodes Processor Configurations PopulatedProcessor Node Block Diagram External Memory Processor Memory ConfigurationInternal Memory 0x0180 DSP Memory Map Nodes B, C, and D AddressHost Port Synchronous Burst SramSynchronous Dram Processor Expansion ModuleProcessor Boot Source Jumpers Node Processor BootingSerial Port Routing Serial Port RoutingVME and PMC Connections for Serial Port PEM Connections for Serial Port 0Arbitration Global Shared Bus Access Source TargetGlobal Shared Bus MemoryBurst Cycle Bus Access Single Cycle Bus AccessLocked Cycles Global Shared Bus SCV64 Primary Slave A32/A24 Interface VME64 Bus InterfaceVME Operation A24 Secondary Slave Interface AccessA24 Secondary Interface Memory Map Hpia HPI Register Addresses VME addressMaster A32/A24/A16 SCV64 Interface VME64 Bus Interface DSP~LINK3 Data Transfer Operating Modes DSP~LINK3 InterfaceAstrben Address Strobe Control ModeDSP~LINK3 Reset Interface SignalsDSP~LINK3 Interface PCI Offset Address Hurricane ConfigurationPCI Interface Value Initialize Hurricane Register SetBCC2A PCI Device Hurricane ImplementationJtag Chain Jtag DebuggingJtag Debugging Overview Interrupt HandlingInterrupt Routing DSP~LINK3 Interrupts to Node aSCV64 Interrupt PEM InterruptsPCI Bus Interrupts Hurricane InterruptKIPL2 KIPL1 KIPL0 Kipl Status Bits and the Iack CycleBit Node Whose Access Caused the Bus Error Bus Error InterruptsVME Host Interrupts To Any Node Inter-processor InterruptsRegisters Register Address Summary Access Privilege BusKFC2..0 KSIZE1..0 KADDR1..0 Vpage RegisterVstatus Register KIPL2..0 BuserraKavec Vinta Register Vintb Register Vintc Register Vintd Register Kiplenb Kipl Enable RegisterKiplend KiplencDSP~LINK3 Register DL3RESETID Register Hintc VME A24 Status RegisterHinta HintbVME A24 Control Register Registers Monaco67 SpecificationsBoard Identification MonacoGeneral Specifications ParameterPerformance and Data Throughput Data Access/Transfer PerformanceSpecifications Connector Layout Connector PinoutsVME P1 Connector Pinout VME ConnectorsVME P2 Connector Pinout PMC to VME P2 VME P2 Connector DSP~LINK3 to VME P2 PMC Connector JN1 Pinout PMC ConnectorsPMC Connector JN2 PMC Connector JN4 Non-standard PMC Connector JN5 PEM 1 Connector Pinout PEM ConnectorsPEM 2 Connector Pinout Jtag OUT Connector Jtag ConnectorsJtag in Connector Pinout Connector Pinouts SCV64 Register Initialization Appendix a SCV64 Register ValuesSCV64 Register Initialization VME IndexInterrupts to node A, 40 register Reset Jtag Sysreset