Spectrum Brands C6x VME64 manual Master A32/A24/A16 SCV64 Interface

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Spectrum Signal Processing	Monaco Technical Reference
	VME64 Bus Interface

Before a host can transfer data through a node’s HPI, the VME host must set the HWOB bit of the node’s HPIC register to “1”. This only has to be done once after the Monaco board is reset. To access an address within a ‘C6x’s memory space, the VME host loads the address into the HPIA register. Data is then transferred through the HPID register.

∙The HPID at offset “8h” auto-increments four bytes after every cycle, allowing it to be used for burst DMA data transfers.

∙The HPID at offset “Ch” does not auto-increment, and is therefore intended for single cycle accesses only.

∙The HPID DMA Space offers a 16K address space to VME hosts which increment their target address during DMA transfers. This allows them to transfer data in blocks of 16K 32-bit words to the HPID register used for DMA transfers.

4.4.Master A32/A24/A16 SCV64 Interface

As a VME master, the Monaco board supports A16, A24, or A32 transactions from any node to the VME64 bus through the SCV64 chip. Any node can program the SCV64’s DMA Controller for VME Master Accesses, and can directly master the VMEbus. Each node has its own VPAGE Register to support the KFC, KSIZE, and upper 12 and lower 2 address bits to the SCV64. The upper 11 bits extend the 20-bit address space of the ‘C6x to the full 32-bit address space of the VME bus. Any node can monitor the status of the /KIPL interrupt lines, BUSERRORs for each node, and KAVEC line by reading the VSTATUS Register.

The Monaco board supports Auto-Syscon capabilities allowing it to become the System Controller board when placed in the leftmost slot of the VME backplane. If it is to be the System Controller it should typically be booted from a PEM module equipped with a boot PROM.

Upon reset, the SCV64 is in Bus-Isolation Mode (BI-Mode) which isolates the SCV64 from the VME64 bus. The SCV64 is released from BI-Mode by a write to the SCV64 Location Monitor from any node of the Monaco board.

Part Number 500-00191	27
Revision 2.00

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Contents Monaco Revision Iii PrefaceDocument Rev Date Changes ChangeHistory Table of Contents Monaco Technical Reference Vii Viii List of Figures Table of Contents List of Tables Xii Features IntroductionProduct Operation Processors PEM InterfacesVME PMCReference Documents General Bus Architecture On-Board Power SupplySysreset Reset ConditionsVME A24 Slave Interface Reset Jtag ResetBoard Layout Board LayoutJumper settings Jumper Settings DescriptionOUT Part Number Processor Nodes Processor Configurations PopulatedProcessor Node Block Diagram Processor Memory Configuration Internal MemoryExternal Memory 0x0180 DSP Memory Map Nodes B, C, and D AddressHost Port Synchronous Burst SramSynchronous Dram Processor Expansion ModuleProcessor Boot Source Jumpers Node Processor BootingSerial Port Routing Serial Port RoutingVME and PMC Connections for Serial Port PEM Connections for Serial Port 0Arbitration Global Shared Bus Access Source TargetGlobal Shared Bus MemoryBurst Cycle Bus Access Single Cycle Bus AccessLocked Cycles Global Shared Bus VME64 Bus Interface VME OperationSCV64 Primary Slave A32/A24 Interface A24 Secondary Slave Interface AccessA24 Secondary Interface Memory Map Hpia HPI Register Addresses VME addressMaster A32/A24/A16 SCV64 Interface VME64 Bus Interface DSP~LINK3 Data Transfer Operating Modes DSP~LINK3 InterfaceAstrben Address Strobe Control ModeDSP~LINK3 Reset Interface SignalsDSP~LINK3 Interface Hurricane Configuration PCI InterfacePCI Offset Address Value Initialize Hurricane Register SetBCC2A PCI Device Hurricane ImplementationJtag Chain Jtag DebuggingJtag Debugging Overview Interrupt HandlingInterrupt Routing DSP~LINK3 Interrupts to Node aSCV64 Interrupt PEM InterruptsPCI Bus Interrupts Hurricane InterruptKIPL2 KIPL1 KIPL0 Kipl Status Bits and the Iack CycleBit Node Whose Access Caused the Bus Error Bus Error InterruptsVME Host Interrupts To Any Node Inter-processor InterruptsRegisters Register Address Summary Access Privilege BusKFC2..0 KSIZE1..0 KADDR1..0 Vpage RegisterVstatus Register Buserra KavecKIPL2..0 Vinta Register Vintb Register Vintc Register Vintd Register Kiplenb Kipl Enable RegisterKiplend KiplencDSP~LINK3 Register DL3RESETID Register Hintc VME A24 Status RegisterHinta HintbVME A24 Control Register Registers Monaco67 SpecificationsBoard Identification MonacoGeneral Specifications ParameterPerformance and Data Throughput Data Access/Transfer PerformanceSpecifications Connector Layout Connector PinoutsVME P1 Connector Pinout VME ConnectorsVME P2 Connector Pinout PMC to VME P2 VME P2 Connector DSP~LINK3 to VME P2 PMC Connector JN1 Pinout PMC ConnectorsPMC Connector JN2 PMC Connector JN4 Non-standard PMC Connector JN5 PEM 1 Connector Pinout PEM ConnectorsPEM 2 Connector Pinout Jtag Connectors Jtag in Connector PinoutJtag OUT Connector Connector Pinouts SCV64 Register Initialization Appendix a SCV64 Register ValuesSCV64 Register Initialization VME IndexInterrupts to node A, 40 register Reset Jtag Sysreset