Spectrum Brands C6x VME64 manual PEM 2 Connector Pinout

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Monaco Technical Reference	Spectrum Signal Processing
Connector Pinouts

Table 24 PEM 2 Connector Pinout

Pin #	Signal	Pin #	Signal

1	GND	2	GND

3	CLKX1	4	ED0

5	FSX1	6	ED1

7	DX1	8	ED2

9	DR1	10	ED3

11	FSR1	12	ED4

13	CLKR1	14	ED5

15	GND	16	ED6

17	CLKS1	18	ED7

19	RSVD	20	GND

21	/PEM_CE2	22	ED8

23	RSVD	24	ED9

25	/HOLD	26	ED10

27	/HOLDA	28	ED11

29	RSVD	30	ED12

31	EA20	32	ED13

33	EA21	34	ED14

35	RSVD	36	ED15

37	+3.3V	38	+5V

39	+3.3V	40	+5V

41	/BE0	42	DMAC0

43	/BE1	44	DMAC1

45	/BE2	46	DMAC2

47	/BE3	48	+12V

49	/SDRAS	50	-12V

51	/SDCAS	52	/PEM_INT2

53	/SDWE	54	RSVD

55	GND	56	GND

57	PEM_TIMER	58	RSVD

59	GND	60	SDA10

72	Part Number 500-00191
	Revision 2.00

Image 84

Contents Monaco Revision Preface IiiDocument Rev Date Changes ChangeHistory Table of Contents Monaco Technical Reference Vii Viii List of Figures Table of Contents List of Tables Xii Features IntroductionProduct Operation Processors Interfaces VMEPMC PEMReference Documents On-Board Power Supply General Bus ArchitectureReset Conditions VME A24 Slave Interface ResetJtag Reset SysresetBoard Layout Board LayoutJumper settings Jumper Settings DescriptionOUT Part Number Processor Configurations Populated Processor NodesProcessor Node Block Diagram Processor Memory Configuration Internal MemoryExternal Memory 0x0180 DSP Memory Map Address Nodes B, C, and DSynchronous Burst Sram Synchronous DramProcessor Expansion Module Host PortProcessor Booting Processor Boot Source Jumpers NodeSerial Port Routing Serial Port RoutingPEM Connections for Serial Port 0 VME and PMC Connections for Serial PortGlobal Shared Bus Access Source Target Global Shared BusMemory ArbitrationSingle Cycle Bus Access Burst Cycle Bus AccessLocked Cycles Global Shared Bus VME64 Bus Interface VME OperationSCV64 Primary Slave A32/A24 Interface Access A24 Secondary Slave InterfaceA24 Secondary Interface Memory Map HPI Register Addresses VME address HpiaMaster A32/A24/A16 SCV64 Interface VME64 Bus Interface DSP~LINK3 Interface DSP~LINK3 Data Transfer Operating ModesAddress Strobe Control Mode AstrbenInterface Signals DSP~LINK3 ResetDSP~LINK3 Interface Hurricane Configuration PCI InterfacePCI Offset Address Hurricane Register Set Value InitializeBCC2A Hurricane Implementation PCI DeviceJtag Debugging Jtag ChainJtag Debugging Interrupt Handling OverviewDSP~LINK3 Interrupts to Node a Interrupt RoutingPEM Interrupts PCI Bus InterruptsHurricane Interrupt SCV64 InterruptKipl Status Bits and the Iack Cycle KIPL2 KIPL1 KIPL0Bus Error Interrupts Bit Node Whose Access Caused the Bus ErrorInter-processor Interrupts VME Host Interrupts To Any NodeRegister Address Summary Access Privilege Bus RegistersVpage Register KFC2..0 KSIZE1..0 KADDR1..0Vstatus Register Buserra KavecKIPL2..0 Vinta Register Vintb Register Vintc Register Vintd Register Kipl Enable Register KiplendKiplenc KiplenbDL3RESET DSP~LINK3 RegisterID Register VME A24 Status Register HintaHintb HintcVME A24 Control Register Registers Specifications Board IdentificationMonaco Monaco67Specifications Parameter GeneralData Access/Transfer Performance Performance and Data ThroughputSpecifications Connector Pinouts Connector LayoutVME Connectors VME P1 Connector PinoutVME P2 Connector Pinout PMC to VME P2 VME P2 Connector DSP~LINK3 to VME P2 PMC Connectors PMC Connector JN1 PinoutPMC Connector JN2 PMC Connector JN4 Non-standard PMC Connector JN5 PEM Connectors PEM 1 Connector PinoutPEM 2 Connector Pinout Jtag Connectors Jtag in Connector PinoutJtag OUT Connector Connector Pinouts Appendix a SCV64 Register Values SCV64 Register InitializationSCV64 Register Initialization Index VMEInterrupts to node A, 40 register Reset Jtag Sysreset