Spectrum Brands C6x VME64 manual VME A24 Status Register, Hinta, Hintb, Hintc, Hintd

Page 68

Monaco Technical Reference

Spectrum Signal Processing

Registers

VME A24 Status Register

VME A24 Secondary Base Address + 1000h

D31..						..D8

		Reserved

D7..	..D4		D3	D2	D1	D0

Reserved			HINT_D	HINT_C	HINT_B	HINT_A

The VME host reads this register to determine the state of the HINT lines from each processor node. Each bit corresponds to one of the four processor nodes. The state of the bit is simply a reflection of the HINT bit value in the corresponding ‘C6x HPIC register. A “1” in the bit position indicates that the corresponding ‘C6x processor has requested an interrupt.

HINT_A	Bit D0 is set to “1” when node A is requesting a host interrupt.
HINT_B	Bit D1 is set to “1” when node B is requesting a host interrupt.
HINT_C	Bit D2 is set to “1” when node C is requesting a host interrupt.
HINT_D	Bit D3 is set to “1” when node D is requesting a host interrupt.

This read only register is accessed from the VME A24 bus. It is located at offset 1000h from the base address set by jumper JP1 (A23..A17).

56	Part Number 500-00191
	Revision 2.00

Image 68

Contents Monaco Revision Preface IiiHistory Document Rev Date ChangesChange Table of Contents Monaco Technical Reference Vii Viii List of Figures Table of Contents List of Tables Xii Product Operation Processors FeaturesIntroduction Interfaces VMEPMC PEMReference Documents On-Board Power Supply General Bus ArchitectureReset Conditions VME A24 Slave Interface ResetJtag Reset SysresetBoard Layout Board LayoutOUT Jumper settingsJumper Settings Description Part Number Processor Configurations Populated Processor NodesProcessor Node Block Diagram External Memory Processor Memory ConfigurationInternal Memory 0x0180 DSP Memory Map Address Nodes B, C, and DSynchronous Burst Sram Synchronous DramProcessor Expansion Module Host PortProcessor Booting Processor Boot Source Jumpers NodeSerial Port Routing Serial Port RoutingPEM Connections for Serial Port 0 VME and PMC Connections for Serial PortGlobal Shared Bus Access Source Target Global Shared BusMemory ArbitrationSingle Cycle Bus Access Burst Cycle Bus AccessLocked Cycles Global Shared Bus SCV64 Primary Slave A32/A24 Interface VME64 Bus InterfaceVME Operation Access A24 Secondary Slave InterfaceA24 Secondary Interface Memory Map HPI Register Addresses VME address HpiaMaster A32/A24/A16 SCV64 Interface VME64 Bus Interface DSP~LINK3 Interface DSP~LINK3 Data Transfer Operating ModesAddress Strobe Control Mode AstrbenInterface Signals DSP~LINK3 ResetDSP~LINK3 Interface PCI Offset Address Hurricane ConfigurationPCI Interface Hurricane Register Set Value InitializeBCC2A Hurricane Implementation PCI DeviceJtag Debugging Jtag ChainJtag Debugging Interrupt Handling OverviewDSP~LINK3 Interrupts to Node a Interrupt RoutingPEM Interrupts PCI Bus InterruptsHurricane Interrupt SCV64 InterruptKipl Status Bits and the Iack Cycle KIPL2 KIPL1 KIPL0Bus Error Interrupts Bit Node Whose Access Caused the Bus ErrorInter-processor Interrupts VME Host Interrupts To Any NodeRegister Address Summary Access Privilege Bus RegistersVpage Register KFC2..0 KSIZE1..0 KADDR1..0Vstatus Register KIPL2..0 BuserraKavec Vinta Register Vintb Register Vintc Register Vintd Register Kipl Enable Register KiplendKiplenc KiplenbDL3RESET DSP~LINK3 RegisterID Register VME A24 Status Register HintaHintb HintcVME A24 Control Register Registers Specifications Board IdentificationMonaco Monaco67Specifications Parameter GeneralData Access/Transfer Performance Performance and Data ThroughputSpecifications Connector Pinouts Connector LayoutVME Connectors VME P1 Connector PinoutVME P2 Connector Pinout PMC to VME P2 VME P2 Connector DSP~LINK3 to VME P2 PMC Connectors PMC Connector JN1 PinoutPMC Connector JN2 PMC Connector JN4 Non-standard PMC Connector JN5 PEM Connectors PEM 1 Connector PinoutPEM 2 Connector Pinout Jtag OUT Connector Jtag ConnectorsJtag in Connector Pinout Connector Pinouts Appendix a SCV64 Register Values SCV64 Register InitializationSCV64 Register Initialization Index VMEInterrupts to node A, 40 register Reset Jtag Sysreset