Spectrum Brands C6x VME64 manual Locked Cycles

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Spectrum Signal Processing	Monaco Technical Reference
	Global Shared Bus

Although this is a non-prioritized scheme, the back-off function of the SCV64 interface resolves collisions between a bus master and the VMEbus if there is contention for the VMEbus.

Note: There are no ownership timers for the Hurricane or SCV64. If the

Hurricane holds the bus too long the VME bus could timeout.

3.2.3.Locked Cycles

A ‘C6x can lock the Global Shared Bus in order to perform Read-Modify-Write (RMW) or other atomic accesses to it, by driving its Timer 0 (TOUT0) low. After the TOUT0 is driven low, the next access to the Global Shared Bus acquires the bus. The bus is not released until the ‘C6x drives the Timer 0 (TOUT0) pin high.

Caution: The capability of locking the Global Shared Bus from a ‘C6x should be used carefully because other devices will not acquire the bus once it is locked. This capability is intended for read-modify-write accesses to the Global Shared RAM and registers. It is highly recommended that Bus locking not be used. It can lead to a deadlock condition, and in particular, result in debugger timeouts.

The following precautions should be observed when locking the Global Shared Bus:

1.VME bus timeouts can occur because the SCV64 cannot access the board while a ‘C6x has locked the bus.

2.If node A accesses the DSP~LINK3 interface while it has locked the Global Shared Bus by asserting TOUT0, the bus will be released. Node A’s next access to the bus will re-lock it to node A, providing that TOUT0 is still asserted.

3.Some SCV64 inbound cycles can occur while the bus is locked. If a ‘C6x has locked the bus and is performing a VME outbound cycle while a VME inbound cycle is in progress, the ‘C6x will be temporarily backed off and the SCV64 cycle will proceed. The Global Shared Bus will be returned to that ‘C6x node after the SCV64 cycle finishes. No other ‘C6x will get ownership of the bus.

4.If a debugger is being used when one processor has the bus locked for an extended time while another processor is trying to get the bus, the debugger may timeout.

Part Number 500-00191	21
Revision 2.00

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Contents Monaco Revision Iii PrefaceDocument Rev Date Changes ChangeHistory Table of Contents Monaco Technical Reference Vii Viii List of Figures Table of Contents List of Tables Xii Features IntroductionProduct Operation Processors VME InterfacesPMC PEMReference Documents General Bus Architecture On-Board Power SupplyVME A24 Slave Interface Reset Reset ConditionsJtag Reset SysresetBoard Layout Board LayoutJumper settings Jumper Settings DescriptionOUT Part Number Processor Nodes Processor Configurations PopulatedProcessor Node Block Diagram Processor Memory Configuration Internal MemoryExternal Memory 0x0180 DSP Memory Map Nodes B, C, and D AddressSynchronous Dram Synchronous Burst SramProcessor Expansion Module Host PortProcessor Boot Source Jumpers Node Processor BootingSerial Port Routing Serial Port Routing VME and PMC Connections for Serial Port PEM Connections for Serial Port 0Global Shared Bus Global Shared Bus Access Source TargetMemory ArbitrationBurst Cycle Bus Access Single Cycle Bus AccessLocked Cycles Global Shared Bus VME64 Bus Interface VME OperationSCV64 Primary Slave A32/A24 Interface A24 Secondary Slave Interface AccessA24 Secondary Interface Memory Map Hpia HPI Register Addresses VME addressMaster A32/A24/A16 SCV64 Interface VME64 Bus Interface DSP~LINK3 Data Transfer Operating Modes DSP~LINK3 InterfaceAstrben Address Strobe Control ModeDSP~LINK3 Reset Interface SignalsDSP~LINK3 Interface Hurricane Configuration PCI InterfacePCI Offset Address Value Initialize Hurricane Register SetBCC2A PCI Device Hurricane ImplementationJtag Chain Jtag DebuggingJtag Debugging Overview Interrupt HandlingInterrupt Routing DSP~LINK3 Interrupts to Node aPCI Bus Interrupts PEM InterruptsHurricane Interrupt SCV64 InterruptKIPL2 KIPL1 KIPL0 Kipl Status Bits and the Iack CycleBit Node Whose Access Caused the Bus Error Bus Error InterruptsVME Host Interrupts To Any Node Inter-processor InterruptsRegisters Register Address Summary Access Privilege BusKFC2..0 KSIZE1..0 KADDR1..0 Vpage RegisterVstatus Register Buserra KavecKIPL2..0 Vinta Register Vintb Register Vintc Register Vintd Register Kiplend Kipl Enable RegisterKiplenc KiplenbDSP~LINK3 Register DL3RESETID Register Hinta VME A24 Status RegisterHintb HintcVME A24 Control Register Registers Board Identification SpecificationsMonaco Monaco67General Specifications ParameterPerformance and Data Throughput Data Access/Transfer PerformanceSpecifications Connector Layout Connector PinoutsVME P1 Connector Pinout VME ConnectorsVME P2 Connector Pinout PMC to VME P2 VME P2 Connector DSP~LINK3 to VME P2 PMC Connector JN1 Pinout PMC ConnectorsPMC Connector JN2 PMC Connector JN4 Non-standard PMC Connector JN5 PEM 1 Connector Pinout PEM ConnectorsPEM 2 Connector Pinout Jtag Connectors Jtag in Connector PinoutJtag OUT Connector Connector Pinouts SCV64 Register Initialization Appendix a SCV64 Register ValuesSCV64 Register Initialization VME IndexInterrupts to node A, 40 register Reset Jtag Sysreset