Spectrum Brands C6x VME64 manual Kipl Status Bits and the Iack Cycle, KIPL2 KIPL1 KIPL0

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Monaco Technical Reference

Spectrum Signal Processing

Interrupt Handling

The /KIPL[2..0] status bits, D[2..0], in the VSTATUS Register indicate the priority level of the SCV64 interrupt. These bits reflect the state of the /KIPL lines from the SCV64. If all three active-low bits are set to “1” (inactive), then an SCV64 interrupt did not cause the INT4 interrupt.

If the interrupt was due to an SCV64 interrupt, it is serviced by performing an IACK cycle to the SCV64. An IACK cycle is a special type of VME read cycle to a specific location in the IACK cycle space (base address 016F 0000h).

For an IACK read cycle, bits D[0..7] of the VPAGE Register must be initialized in the following way:

∙KADDR0 (bit D0) is set to “0”

∙The value of the /KIPL0 bit in the VSTATUS Register is inverted and placed in the KADDR1 bit (bit D1)

∙KSIZE0 (bit D2) is set to “1”

∙KSIZE1 (bit D3) is set to “0”

∙All three KFC bits (bits D[6..4]) are set to “1”

The /KIPL[2..1] status bits, D[2..1], in the VSTATUS Register determine the offset of the address to read within the IACK cycle space.

∙/KIPL2 is inverted to determine IACK address bit A3

∙/KIPL1 is inverted to determine IACK address bit A2

The following table summarizes how the /KIPL[2..1] bits in the VSTATUS Register initialize the VPAGE Register and set the IACK cycle address.

Table 12 KIPL Status Bits and the IACK Cycle

/KIPL2	/KIPL1	/KIPL0	VPAGE KADDR1	IACK Address

1	1	1	Not Used	Not Used

1	1	0	1	016F	0000h

1	0	1	0	016F	0004h

1	0	0	1	016F	0004h

0	1	1	0	016F	0008h

0	1	0	1	016F	0008h

0	0	1	0	016F	000Ch

0	0	0	1	016F	000Ch

42	Part Number 500-00191
	Revision 2.00

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Contents Monaco Revision Preface IiiDocument Rev Date Changes ChangeHistory Table of Contents Monaco Technical Reference Vii Viii List of Figures Table of Contents List of Tables Xii Features IntroductionProduct Operation Processors PMC InterfacesVME PEMReference Documents On-Board Power Supply General Bus ArchitectureJtag Reset Reset ConditionsVME A24 Slave Interface Reset SysresetBoard Layout Board LayoutJumper settings Jumper Settings DescriptionOUT Part Number Processor Configurations Populated Processor NodesProcessor Node Block Diagram Processor Memory Configuration Internal MemoryExternal Memory 0x0180 DSP Memory Map Address Nodes B, C, and DProcessor Expansion Module Synchronous Burst SramSynchronous Dram Host PortProcessor Booting Processor Boot Source Jumpers NodeSerial Port Routing Serial Port RoutingPEM Connections for Serial Port 0 VME and PMC Connections for Serial PortMemory Global Shared Bus Access Source TargetGlobal Shared Bus ArbitrationSingle Cycle Bus Access Burst Cycle Bus AccessLocked Cycles Global Shared Bus VME64 Bus Interface VME OperationSCV64 Primary Slave A32/A24 Interface Access A24 Secondary Slave InterfaceA24 Secondary Interface Memory Map HPI Register Addresses VME address HpiaMaster A32/A24/A16 SCV64 Interface VME64 Bus Interface DSP~LINK3 Interface DSP~LINK3 Data Transfer Operating ModesAddress Strobe Control Mode AstrbenInterface Signals DSP~LINK3 ResetDSP~LINK3 Interface Hurricane Configuration PCI InterfacePCI Offset Address Hurricane Register Set Value InitializeBCC2A Hurricane Implementation PCI DeviceJtag Debugging Jtag ChainJtag Debugging Interrupt Handling OverviewDSP~LINK3 Interrupts to Node a Interrupt RoutingHurricane Interrupt PEM InterruptsPCI Bus Interrupts SCV64 InterruptKipl Status Bits and the Iack Cycle KIPL2 KIPL1 KIPL0Bus Error Interrupts Bit Node Whose Access Caused the Bus ErrorInter-processor Interrupts VME Host Interrupts To Any NodeRegister Address Summary Access Privilege Bus RegistersVpage Register KFC2..0 KSIZE1..0 KADDR1..0Vstatus Register Buserra KavecKIPL2..0 Vinta Register Vintb Register Vintc Register Vintd Register Kiplenc Kipl Enable RegisterKiplend KiplenbDL3RESET DSP~LINK3 RegisterID Register Hintb VME A24 Status RegisterHinta HintcVME A24 Control Register Registers Monaco SpecificationsBoard Identification Monaco67Specifications Parameter GeneralData Access/Transfer Performance Performance and Data ThroughputSpecifications Connector Pinouts Connector LayoutVME Connectors VME P1 Connector PinoutVME P2 Connector Pinout PMC to VME P2 VME P2 Connector DSP~LINK3 to VME P2 PMC Connectors PMC Connector JN1 PinoutPMC Connector JN2 PMC Connector JN4 Non-standard PMC Connector JN5 PEM Connectors PEM 1 Connector PinoutPEM 2 Connector Pinout Jtag Connectors Jtag in Connector PinoutJtag OUT Connector Connector Pinouts Appendix a SCV64 Register Values SCV64 Register InitializationSCV64 Register Initialization Index VMEInterrupts to node A, 40 register Reset Jtag Sysreset