Spectrum Brands C6x VME64 manual Vpage Register, KFC2..0 KSIZE1..0 KADDR1..0

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Monaco Technical Reference

Spectrum Signal Processing

Registers

VPAGE Register

Address: 016D 0000h

D31..							..D24

			Reserved

D23..			..D20	D19	D18	D17	D16

	Reserved			KADDR31	KADDR30	KADDR29	KADDR28

D15	D14	D13	D12	D11	D10	D9	D8

KADDR27	KADDR26	KADDR25	KADDR24	KADDR23	KADDR22	KADDR21	KADDR20


D7	D6	D5	D4	D3	D2	D1	D0

Reserved	KFC2	KFC1	KFC0	KSIZE1	KSIZE0	KADDR1	KADDR0

This register sets certain SCV64 address and control lines in order to extend the address range of the ‘C6x processors and set up the type of VME cycle to be performed. Each node has its own register. Except for D7 all other reserved bits are disconnected; D7 will store what is written to it. These register is undefined upon reset and should be initialized. Refer to the SCV64 User Manual for complete information on these signals.

KADDR[31..20] Sets the upper 12 address bits that are latched to the SCV64 when the ‘C6x accesses the VME address space. This extends the 20 address bits

of the ‘C6x to the full 32 bits of the VME address space. This allows a ‘C6x access the entire VME bus as a master by setting these bits to

1 Mbyte region being accessed. A write to this register latches data lines D19..8 and presents them to the SCV64 upper address lines KADDR31..20 respectively. For example, a write to the VPAGE register with data equal to 8 0000h causes the next outbound VME cycle (base address 0170 0000h) with offset 0x0 to be addressed at VME address 8000 0000h.

KFC[2..0]

KSIZE[1..0]

KADDR[1..0]

Sets the access type as User or Supervisor Program, or Data accesses. Directly affects the address modifiers used for the VME Master cycle.

Sets the number of bytes transferred for VME Master cycles. Directly affects D32, D16, or D8 access type.

These bits allow the node, which is little endian in order to access the PEM and PMCs, to access the SCV64, which is big endian.

Note: Although access to VPAGE is local to each processor node, any read or write to the register requires that the Global Shared Bus to be acquired. The DSP’s cycles are extended until any current Global Shared Bus operations are complete when accessing the VPAGE Register.

46	Part Number 500-00191
	Revision 2.00

Image 58

Contents Monaco Revision Preface IiiChange Document Rev Date ChangesHistory Table of Contents Monaco Technical Reference Vii Viii List of Figures Table of Contents List of Tables Xii Introduction FeaturesProduct Operation Processors PMC InterfacesVME PEMReference Documents On-Board Power Supply General Bus ArchitectureJtag Reset Reset ConditionsVME A24 Slave Interface Reset SysresetBoard Layout Board LayoutJumper Settings Description Jumper settingsOUT Part Number Processor Configurations Populated Processor NodesProcessor Node Block Diagram Internal Memory Processor Memory ConfigurationExternal Memory 0x0180 DSP Memory Map Address Nodes B, C, and DProcessor Expansion Module Synchronous Burst SramSynchronous Dram Host PortProcessor Booting Processor Boot Source Jumpers NodeSerial Port Routing Serial Port RoutingPEM Connections for Serial Port 0 VME and PMC Connections for Serial PortMemory Global Shared Bus Access Source TargetGlobal Shared Bus ArbitrationSingle Cycle Bus Access Burst Cycle Bus AccessLocked Cycles Global Shared Bus VME Operation VME64 Bus InterfaceSCV64 Primary Slave A32/A24 Interface Access A24 Secondary Slave InterfaceA24 Secondary Interface Memory Map HPI Register Addresses VME address HpiaMaster A32/A24/A16 SCV64 Interface VME64 Bus Interface DSP~LINK3 Interface DSP~LINK3 Data Transfer Operating ModesAddress Strobe Control Mode AstrbenInterface Signals DSP~LINK3 ResetDSP~LINK3 Interface PCI Interface Hurricane ConfigurationPCI Offset Address Hurricane Register Set Value InitializeBCC2A Hurricane Implementation PCI DeviceJtag Debugging Jtag ChainJtag Debugging Interrupt Handling OverviewDSP~LINK3 Interrupts to Node a Interrupt RoutingHurricane Interrupt PEM InterruptsPCI Bus Interrupts SCV64 InterruptKipl Status Bits and the Iack Cycle KIPL2 KIPL1 KIPL0Bus Error Interrupts Bit Node Whose Access Caused the Bus ErrorInter-processor Interrupts VME Host Interrupts To Any NodeRegister Address Summary Access Privilege Bus RegistersVpage Register KFC2..0 KSIZE1..0 KADDR1..0Vstatus Register Kavec BuserraKIPL2..0 Vinta Register Vintb Register Vintc Register Vintd Register Kiplenc Kipl Enable RegisterKiplend KiplenbDL3RESET DSP~LINK3 RegisterID Register Hintb VME A24 Status RegisterHinta HintcVME A24 Control Register Registers Monaco SpecificationsBoard Identification Monaco67Specifications Parameter GeneralData Access/Transfer Performance Performance and Data ThroughputSpecifications Connector Pinouts Connector LayoutVME Connectors VME P1 Connector PinoutVME P2 Connector Pinout PMC to VME P2 VME P2 Connector DSP~LINK3 to VME P2 PMC Connectors PMC Connector JN1 PinoutPMC Connector JN2 PMC Connector JN4 Non-standard PMC Connector JN5 PEM Connectors PEM 1 Connector PinoutPEM 2 Connector Pinout Jtag in Connector Pinout Jtag ConnectorsJtag OUT Connector Connector Pinouts Appendix a SCV64 Register Values SCV64 Register InitializationSCV64 Register Initialization Index VMEInterrupts to node A, 40 register Reset Jtag Sysreset