Spectrum Brands C6x VME64 manual HPI Register Addresses VME address, Hpia

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Monaco Technical Reference

Spectrum Signal Processing

VME64 Bus Interface

The Host Port Interface (HPI) allows a VME host to access the memory map of any ‘C6X. The board transfers 32-bit VME accesses automatically through the 16-bit Host Port Interface as two 16-bit words. The interface consists of three read/write, 32-bit registers that are accessed through the VME A24 slave interface:

∙HPI Address register (HPIA)

∙HPI Control register (HPIC). A ‘C6x can also read and write to its HPI Control register (HPIC) at address 0188 0000h.

∙HPI Data register (HPID)

VME address bits A[3:2] select which register is being accessed in each node’s HPI register address space. These bits are mapped to the HCNTRL[1:0] control pins of the ‘C6x. The following table shows how the HPI interface is addressed.

Table 9 HPI Register Addresses

		VME address

‘C6x	Node	Node	Node	Node
Register	A	B	C	D	Description

HPIC	00 2000h	00 3000h	00 4000h	00 5000h	State for reading/setting the Control Register value.

HPIA	00 2004h	00 3004h	00 4004h	00 5004h	Used to read/set the HPI address pointer. The HPIA
					points into the C6x memory space.

HPID	00 2008h	00 3008h	00 4008h	00 5008h	A VME host reads and writes data to this address for
					DMA transfers to the HPID register. The HPIA register
					automatically increments by 4 bytes as each word is
					transferred through the HPID register.

HPID	00 200Ch	00 300Ch	00 400Ch	00 500Ch	A VME host reads and writes data to this address for
					single cycle transfers to the HPID register. The HPIA is
					not incremented for this HPI access mode.


HPID	01 0000h	01 4000h	01 8000h	01 C0000h	VME hosts which increment their target address can use
DMA					this address space for DMA transfers to the HPID
Space					register. Up to 4K of 32-bit data can be transferred in this
					space. Data written to this space is automatically
					transferred to the HPID register, and the HPIA register
					automatically increments by 4 bytes as each word is
					transferred.

26	Part Number 500-00191
	Revision 2.00

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Contents Monaco Revision Preface IiiHistory Document Rev Date ChangesChange Table of Contents Monaco Technical Reference Vii Viii List of Figures Table of Contents List of Tables Xii Product Operation Processors FeaturesIntroduction PMC InterfacesVME PEMReference Documents On-Board Power Supply General Bus ArchitectureJtag Reset Reset ConditionsVME A24 Slave Interface Reset SysresetBoard Layout Board LayoutOUT Jumper settingsJumper Settings Description Part Number Processor Configurations Populated Processor NodesProcessor Node Block Diagram External Memory Processor Memory ConfigurationInternal Memory 0x0180 DSP Memory Map Address Nodes B, C, and DProcessor Expansion Module Synchronous Burst SramSynchronous Dram Host PortProcessor Booting Processor Boot Source Jumpers NodeSerial Port Routing Serial Port RoutingPEM Connections for Serial Port 0 VME and PMC Connections for Serial PortMemory Global Shared Bus Access Source TargetGlobal Shared Bus ArbitrationSingle Cycle Bus Access Burst Cycle Bus AccessLocked Cycles Global Shared Bus SCV64 Primary Slave A32/A24 Interface VME64 Bus InterfaceVME Operation Access A24 Secondary Slave InterfaceA24 Secondary Interface Memory Map HPI Register Addresses VME address HpiaMaster A32/A24/A16 SCV64 Interface VME64 Bus Interface DSP~LINK3 Interface DSP~LINK3 Data Transfer Operating ModesAddress Strobe Control Mode AstrbenInterface Signals DSP~LINK3 ResetDSP~LINK3 Interface PCI Offset Address Hurricane ConfigurationPCI Interface Hurricane Register Set Value InitializeBCC2A Hurricane Implementation PCI DeviceJtag Debugging Jtag ChainJtag Debugging Interrupt Handling OverviewDSP~LINK3 Interrupts to Node a Interrupt RoutingHurricane Interrupt PEM InterruptsPCI Bus Interrupts SCV64 InterruptKipl Status Bits and the Iack Cycle KIPL2 KIPL1 KIPL0Bus Error Interrupts Bit Node Whose Access Caused the Bus ErrorInter-processor Interrupts VME Host Interrupts To Any NodeRegister Address Summary Access Privilege Bus RegistersVpage Register KFC2..0 KSIZE1..0 KADDR1..0Vstatus Register KIPL2..0 BuserraKavec Vinta Register Vintb Register Vintc Register Vintd Register Kiplenc Kipl Enable RegisterKiplend KiplenbDL3RESET DSP~LINK3 RegisterID Register Hintb VME A24 Status RegisterHinta HintcVME A24 Control Register Registers Monaco SpecificationsBoard Identification Monaco67Specifications Parameter GeneralData Access/Transfer Performance Performance and Data ThroughputSpecifications Connector Pinouts Connector LayoutVME Connectors VME P1 Connector PinoutVME P2 Connector Pinout PMC to VME P2 VME P2 Connector DSP~LINK3 to VME P2 PMC Connectors PMC Connector JN1 PinoutPMC Connector JN2 PMC Connector JN4 Non-standard PMC Connector JN5 PEM Connectors PEM 1 Connector PinoutPEM 2 Connector Pinout Jtag OUT Connector Jtag ConnectorsJtag in Connector Pinout Connector Pinouts Appendix a SCV64 Register Values SCV64 Register InitializationSCV64 Register Initialization Index VMEInterrupts to node A, 40 register Reset Jtag Sysreset