Spectrum Brands C6x VME64 manual PEM Interrupts, PCI Bus Interrupts, Hurricane Interrupt, Bit

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Spectrum Signal Processing	Monaco Technical Reference
	Interrupt Handling

8.3.PEM Interrupts

There are two active-low, driven interrupts from the PEM connectors for each node. These interrupts (/PEM INT1 and /PEM INT2) are OR’ed together. Their output is routed to INT6 of each node’s DSP and inverted to create a rising-edge trigger.

The Monaco board does not latch the PEM interrupts. They must be cleared on the PEM module that generated them.

8.4.PCI Bus Interrupts

The four active-low interrupt signals from the PCI bus (INTA#, INTB#, INTC#, and INTD#) are physically tied together and routed to INT5 of each of ‘C6x DSPs. They are also buffered through a de-bounce circuit because they are open-collector. On node A the PCI bus interrupt is also shared with the Hurricane interrupt on INT5 of the ‘C6x through an OR gate.

The interrupt is not latched, and its source must be cleared on the PMC module.

8.5.Hurricane Interrupt

The interrupt signal from the Hurricane chip is routed to each of the board’s ‘C6x processors. On node A the PCI bus interrupt is also shared with the Hurricane interrupt on INT5 of the ‘C6x through an OR gate. For nodes B, C, and D, the Hurricane interrupt is routed to INT7 of the ‘C6x.

8.6.SCV64 Interrupt

An interrupt line from the SCV64 VME interface is routed to the INT4 interrupt input of all four ‘C6x processors. The interrupt provides VME, SCV64 timers and DMA, and other local interrupt capability. On-board logic routes VME bus error and the inter- processor VINTx interrupts to INT4 as well.

This interrupt can be individually enabled or disabled for each node using the

KIPL Enable Register (address 016D 8014h). Bits D0..D4 enable the interrupt for each node when set to “1”. The SCV64 interrupt is disabled from reaching the node when the corresponding bit is set to “0”.

Bit	Interrupted Node
D0	Node A
D1	Node B
D2	Node C
D3	Node D

Part Number 500-00191	41
Revision 2.00

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Contents Monaco Revision Iii PrefaceHistory Document Rev Date ChangesChange Table of Contents Monaco Technical Reference Vii Viii List of Figures Table of Contents List of Tables Xii Product Operation Processors FeaturesIntroduction VME InterfacesPMC PEMReference Documents General Bus Architecture On-Board Power SupplyVME A24 Slave Interface Reset Reset ConditionsJtag Reset SysresetBoard Layout Board LayoutOUT Jumper settingsJumper Settings Description Part Number Processor Nodes Processor Configurations PopulatedProcessor Node Block Diagram External Memory Processor Memory ConfigurationInternal Memory 0x0180 DSP Memory Map Nodes B, C, and D AddressSynchronous Dram Synchronous Burst SramProcessor Expansion Module Host PortProcessor Boot Source Jumpers Node Processor BootingSerial Port Routing Serial Port RoutingVME and PMC Connections for Serial Port PEM Connections for Serial Port 0Global Shared Bus Global Shared Bus Access Source TargetMemory ArbitrationBurst Cycle Bus Access Single Cycle Bus AccessLocked Cycles Global Shared Bus SCV64 Primary Slave A32/A24 Interface VME64 Bus InterfaceVME Operation A24 Secondary Slave Interface AccessA24 Secondary Interface Memory Map Hpia HPI Register Addresses VME addressMaster A32/A24/A16 SCV64 Interface VME64 Bus Interface DSP~LINK3 Data Transfer Operating Modes DSP~LINK3 InterfaceAstrben Address Strobe Control ModeDSP~LINK3 Reset Interface SignalsDSP~LINK3 Interface PCI Offset Address Hurricane ConfigurationPCI Interface Value Initialize Hurricane Register SetBCC2A PCI Device Hurricane ImplementationJtag Chain Jtag Debugging Jtag Debugging Overview Interrupt HandlingInterrupt Routing DSP~LINK3 Interrupts to Node aPCI Bus Interrupts PEM InterruptsHurricane Interrupt SCV64 InterruptKIPL2 KIPL1 KIPL0 Kipl Status Bits and the Iack CycleBit Node Whose Access Caused the Bus Error Bus Error InterruptsVME Host Interrupts To Any Node Inter-processor InterruptsRegisters Register Address Summary Access Privilege BusKFC2..0 KSIZE1..0 KADDR1..0 Vpage RegisterVstatus Register KIPL2..0 BuserraKavec Vinta Register Vintb Register Vintc Register Vintd Register Kiplend Kipl Enable RegisterKiplenc KiplenbDSP~LINK3 Register DL3RESETID Register Hinta VME A24 Status RegisterHintb HintcVME A24 Control Register Registers Board Identification SpecificationsMonaco Monaco67General Specifications ParameterPerformance and Data Throughput Data Access/Transfer PerformanceSpecifications Connector Layout Connector PinoutsVME P1 Connector Pinout VME ConnectorsVME P2 Connector Pinout PMC to VME P2 VME P2 Connector DSP~LINK3 to VME P2 PMC Connector JN1 Pinout PMC ConnectorsPMC Connector JN2 PMC Connector JN4 Non-standard PMC Connector JN5 PEM 1 Connector Pinout PEM ConnectorsPEM 2 Connector Pinout Jtag OUT Connector Jtag ConnectorsJtag in Connector Pinout Connector Pinouts SCV64 Register Initialization Appendix a SCV64 Register ValuesSCV64 Register Initialization VME IndexInterrupts to node A, 40 register Reset Jtag Sysreset