AMD SB600 manual

AMD SB600 Register Reference Manual (Public Version)

Technical Reference Manual

Rev. 3.03

P/N: 46155_sb600_rrg_pub_3.03

Contents

Main AMD SB600 Register Reference Manual (Public Version) Page Table of Contents Page Page List of Tables 1 Introduction 1.1 About this Manual 1.2 Nomenclature and Conventions Hexadecimal numbers are prefixed with 0x or suffixed with h, whenever there is a possibility Registers (or fields) of an identical function are sometimes indicated by a single expression in Page 1.3 Features of the SB600 Page 1.4 Block Diagrams SMBUS /ACPI AC97 Audio IDE LPC Figure 2 SB600 PCI Internal Devices and Major Function Blocks 2 Register Descriptions: PCI Devices 2.1 SATA Registers (Device 18, Function 0) SATA AMD SB600 Register Reference Manual Proprietary Page 14 Vendor ID - R - 16 bits - [PCI_Reg:00h] Device ID - R - 16 bits - [PCI_Reg:02h] Command - RW - 16 bits - [PCI_Reg:04h] AMD SB600 Register Reference Manual Proprietary Page 15 Status - RW - 16 bits - [PCI_Reg:06h] Reserved. Revision ID/Class Code- R - 32 bits - [PCI_Reg:08h] Page Page Min_gnt - R - 8 bits - [PCI_Reg:3Eh] Max_latency - R - 8 bits - [PCI_Reg:3Fh] Misc Control - RW - 32 bits - [PCI_Reg:40h] Watch Dog Control And Status - RW - 16 bits - [PCI_Reg:44h] Watch Dog Counter - RW - 16 bits - [PCI_Reg:46h] Page PCI Power Management Control And Status - RW- 16 bits - [PCI_Reg:64h] Serial ATA Capability Register 0 - R- 32 bits - [PCI_Reg:70h] Serial ATA Capability Register 1 - R- 32 bits - [PCI_Reg:74h] IDP Index Register - RW- 32 bits - [PCI_Reg:78h] IDP Data Register - RW- 32 bits - [PCI_Reg:7Ch] AMD SB600 Register Reference Manual Proprietary Page 21 PHY Port0 Control - RW- 32 bits - [PCI_Reg:88h] PHY Port1 Control - RW- 32 bits - [PCI_Reg:8Ch] AMD SB600 Register Reference Manual Proprietary Page 22 PHY Port1 Control - RW- 32 bits - [PCI_Reg:8Ch] PHY Port2 Control - RW- 32 bits - [PCI_Reg:90h] AMD SB600 Register Reference Manual Proprietary Page 23 PHY Port3 Control - RW- 32 bits - [PCI_Reg:94h] BIST Pattern Count - RW - 32 bits - [PCI_Reg:C0h] PCI Target Control TimeOut Counter - RW 8 bits - [PCI_Reg:C4h] Page Page Page AMD SB600 Register Reference Manual Proprietary Page 27 HBA Capabilities R - 32bits [Mem_reg: ABAR + 00h] AMD SB600 Register Reference Manual Proprietary Page 28 HBA Capabilities R - 32bits [Mem_reg: ABAR + 00h] Global HBA Control RW - 32bits [Mem_reg: ABAR + 04h] AMD SB600 Register Reference Manual Proprietary Page 29 Global HBA Control RW - 32bits [Mem_reg: ABAR + 04h] Interrupt Status - RW -32 bits [Mem_reg: ABAR + 08h] Ports Implemented Register - R -32 bits [Mem_reg: ABAR + 0Ch] AHCI Version- R 32 bits [Mem_reg: ABAR + 10h] AMD SB600 Register Reference Manual Proprietary Page 30 Command Completion Coalescing Control(CCC_CTL) - RW 32 bits [Mem_reg: ABAR + 14h] Command Completion Coalescing Ports - RW 32 bits [Mem_reg: ABAR + 18h] Page AMD SB600 Register Reference Manual Proprietary Page 32 Port-N FIS Base Address Upper RW 32 bits [Mem_reg: ABAR + port offset + 0Ch] PortN Interrupt Status - RW - 32 bits [Mem_reg: ABAR + port offset + 10h] AMD SB600 Register Reference Manual Proprietary Page 33 PortN Interrupt Status - RW - 32 bits [Mem_reg: ABAR + port offset + 10h] Port-N Interrupt Enable - RW -32 bits [Mem_reg: ABAR + port offset + 14h] AMD SB600 Register Reference Manual Proprietary Page 34 Port-N Interrupt Enable - RW -32 bits [Mem_reg: ABAR + port offset + 14h] Port-N Command and Status - R - 32 bits [Mem_reg: ABAR + port offset + 18h] Page Page Page AMD SB600 Register Reference Manual Proprietary Page 38 Port-N Task Fike Data R 32 bits [Mem_reg: ABAR + port offset + 20h] Port-N Signature R 32 bits [Mem_reg: ABAR + port offset + 24h] Port-N Serial ATA Status R 32 bits [Mem_reg: ABAR + port offset + 28h] AMD SB600 Register Reference Manual Proprietary Page 39 Port-N Serial ATA Status R 32 bits [Mem_reg: ABAR + port offset + 28h] Port-N Serial ATA Control RW 32 bits [Mem_reg: ABAR + port offset + 2Ch] AMD SB600 Register Reference Manual Proprietary Page 40 Port-N Serial ATA Control RW 32 bits [Mem_reg: ABAR + port offset + 2Ch] AMD SB600 Register Reference Manual Proprietary Page 41 Port-N Serial ATA Error RW 32 bits [Mem_reg: ABAR + port offset + 30h] AMD SB600 Register Reference Manual Proprietary Page 42 Port-N Serial ATA Error RW 32 bits [Mem_reg: ABAR + port offset + 30h] AMD SB600 Register Reference Manual Proprietary Page 43 Port-N Serial ATA Active RW 32 bits [Mem_reg: ABAR + port offset + 34h] Port-N Command Issue RW 32 bits [Mem_reg: ABAR + port offset + 38h] Port- N SNotification RWC 32 bits [Mem_reg: ABAR + port offset + 3Ch] 2.2 OCHI USB 1.1 and EHCI USB 2.0 Controllers USB Page Device / Vendor ID R - 32 bits - [PCI_Reg : 00h] Command RW - 16 bits - [PCI_Reg : 04h] Status R - 16 bits - [PCI_Reg : 06h] Status R - 16 bits - [PCI_Reg : 06h] Revision ID / Class Code R - 32 bits - [PCI_Reg : 08h] Miscellaneous RW/R - 32 bits - [PCI_Reg : 0Ch] Bar_OHCI RW - 32 bits - [PCI_Reg : 10h] Bar_OHCI RW - 32 bits - [PCI_Reg : 10h] Subsystem Vendor ID / Subsystem ID RW - 32 bits - [PCI_Reg : 2Ch] Capability Pointer R - 8 bits - [PCI_Reg : 34h] Interrupt Line RW 32 bits - [PCI_Reg : 3Ch] Config Timers / MSI Disable (OHCI0 only) RW - 16 bits - [PCI_Reg : 40h] Config Timers / MSI Disable (OHCI0 only) RW - 16 bits - [PCI_Reg : 40h] Port Disable (OHCI0 only) RW - 16 bits - [PCI_Reg : 42h] OHCI Misc Control (OHCI0 only) RW - 16 bits - [PCI_Reg: 50h] Over Current Control 1 (OHCI0 only) R - 32 bits - [PCI_Reg : 58h] Over Current Control 1 (OHCI0 only) R - 32 bits - [PCI_Reg : 58h] Over Current Control 2 (OHCI0 only) R - 32 bits - [PCI_Reg : 5Ch] OHCI OverCurrent Enable (OHCI0 only) RW - 16 bits - [PCI_Reg : 68h] Page Page Page HcControl - 32 bits - [MEM_Reg : 04h] Reserved HcCommandStatus - 32 bits - [MEM_Reg : 08h] HcCommandStatus - 32 bits - [MEM_Reg : 08h] OwnershipChangeRequest SchedulingOverrunCount HcInterruptStatus RW - 32 bits - [MEM_Reg : 0Ch] HcInterruptEnable - 32 bits - [MEM_Reg : 10h] HcInterruptEnable - 32 bits - [MEM_Reg : 10h] HcInterruptDisable - 32 bits - [MEM_Reg : 14h] HcHCCA - 32 bits - [MEM_Reg : 18h] Page HcBulkCurrentED - 32 bits - [MEM_Reg : 2Ch] HcDoneHead - 32 bits - [MEM_Reg : 30h] HcFmInterval - 32 bits - [MEM_Reg : 34h] FSLargestDataPacket Page HcRhDescriptorA - 32 bits - [MEM_Reg : 48h] NumberDownstreamPorts HcRhDescriptorB - 32 bits - [MEM_Reg : 4Ch] HcRhStatus - 32 bits - [MEM_Reg : 50h] HcRhStatus - 32 bits - [MEM_Reg : 50h] HcRhPortStatus - 32 bits - [MEM_Reg : 50h+4*(1:NDP)] Page Page Page Page Page Page Page DEVICE / VENDOR ID R - 32 bits - [PCI_Reg : 00h] Command RW - 16 bits - [PCI_Reg : 04h] Status R - 16 bits - [PCI_Reg : 06h] Revision ID / Class Code R - 32 bits - [PCI_Reg : 08h] Miscellaneous RW - 32 bits - [PCI_Reg : 0Ch] Page Interrupt Line - RW - 32 bits - [PCI_Reg : 3Ch] EHCI Misc Control RW - 32 bits - [PCI_Reg : 50h] EHCI Misc Control RW - 32 bits - [PCI_Reg : 50h] SBRN R - 8 bits - [PCI_Reg : 60h] FLADJ RW - 8 bits - [PCI_Reg : 61h] PME Control RW - 32 bits - [PCI_Reg : C0h] PME Control RW - 32 bits - [PCI_Reg : C0h] PME Data / Status RW - 32 bits - [PCI_Reg : C4h] Page DBUG_PRT Control R - 32 bits - [PCI_Reg : E4h] USBLEGSUP RW - 32 bits - [PCI_Reg : EECP + 00h] USBLEGCTLSTS RW - 32 bits - [PCI_Reg : EECP + 04h] USBLEGCTLSTS RW - 32 bits - [PCI_Reg : EECP + 04h] 2.2.3.2 Host Controller Capability Registers (MEM_Reg) CAPLENGTH R - 8 bits - [MEM_Reg : 00h] HCIVERSION R - 16 bits - [MEM_Reg : 02h] HCSPARAMS R - 32 bits - [MEM_Reg : 04h] HCSPARAMS R - 32 bits - [MEM_Reg : 04h] HCCPARAMS R - 32 bits - [MEM_Reg : 08h] Page USBCMD RW - 32 bits - [EOR_Reg : EHCI_EOR + 00h] USBCMD RW - 32 bits - [EOR_Reg : EHCI_EOR + 00h] USBSTS - RW - 32 bits - [EOR_Reg : EHCI_EOR + 04h] USBSTS - RW - 32 bits - [EOR_Reg : EHCI_EOR + 04h] USBINTR RW - 32 bits - [EOR_Reg : EHCI_EOR + 08h] FRINDEX RW - 32 bits - [EOR_Reg : EHCI_EOR + 0Ch] CTRLDSSEGMENT RW - 32 bits - [EOR_Reg : EHCI_EOR + 10h] PERIODICLISTBASE RW - 32 bits - [EOR_Reg : EHCI_EOR + 14h] ASYNCLISTADDR RW - 32 bits - [EOR_Reg : EHCI_EOR + 18h] CONFIGFLAG RW - 32 bits - [EOR_Reg : EHCI_EOR + 40h] PORTSC (1-N_PORTS) RW - 32 bits - [EOR_Reg : EHCI_EOR + (44h~68h)] Page Page PORTSC (1-N_PORTS) RW - 32 bits - [EOR_Reg : EHCI_EOR + (44h~68h)] Packet Buffer Threshold Values RW - 32 bits - [EOR_Reg : EHCI_EOR + 84h] USB PHY Status 0 RW - 32 bits - [EOR_Reg: EHCI_EOR + 88h] USB PHY Status 1 RW - 32 bits - [EOR_Reg: EHCI_EOR + 8Ch] USB PHY Status 2 RW - 32 bits - [EOR_Reg: EHCI_EOR + 90h] UTMI Control RW - 32 bits - [EOR_Reg: EHCI_EOR + 94h] UTMI Control RW - 32 bits - [EOR_Reg: EHCI_EOR + 94h] BIST Control / Loopback Test RW - 32 bits - [EOR_Reg : EHCI_EOR + 98h] EOR MISC Control RW - 32 bits - [EOR_Reg : EHCI_EOR + 9Ch] USB Common PHY Calibration RW - 32 bits - [EOR_Reg: EHCI_EOR + A0h] Page Page Page 2.3 SMBus Module and ACPI Block (Device 20, Function 0) USB Bus 0 Dev 20 Function 0 SATA 2.3.1 PCI Configuration Registers and Extended Registers 2.3.1.1 PCIE Configuration Registers VendorID - R - 16 bits - [PCI_Reg: 00h] DeviceID - R - 16 bits - [PCI_Reg: 02h] Command- RW - 16 bits - [PCI_Reg: 04h] Command- RW - 16 bits - [PCI_Reg: 04h] STATUS- RW - 16 bits - [PCI_Reg: 06h] Page Page Page Page GPIO_52_to_49_Cntrl - RW 16 bits - [PCI_Reg: 50h] GPIO_56_to_53_Cntrl - RW 16 bits - [PCI_Reg: 52h] GPIO_60_to_57_Cntrl - RW 16 bits - [PCI_Reg: 54h] GPIO_64_to_61_Cntrl - RW 16 bits - [PCI_Reg: 56h] Page SmartPowerControl1B - RW 8 bits - [PCI_Reg: 5Dh] MiscEnable- RW - 8 bits - [PCI_Reg: 62h] MiscEnable- RW - 8 bits - [PCI_Reg: 62h] AzIntMap- RW - 8 bits - [PCI_Reg: 63h] Features Enable- RW - 32 bits - [PCI_Reg: 64h] Features Enable- RW - 32 bits - [PCI_Reg: 64h] UsbEnable - RW - 8 bits - [PCI_Reg: 68h] UsbEnable - RW - 8 bits - [PCI_Reg: 68h] SeriallrqControl- RW - 8 bits - [PCI_Reg: 69h] RTCProtect- RW - 8 bits - [PCI_Reg: 6Ah] USB Reset- RW - 8 bits - [PCI_Reg: 6Bh] TestMode- RW - 16 bits - [PCI_Reg: 6C] IoApic_Conf- RW - 32 bits - [PCI_Reg: 74h] IoAddrEnable - RW - 32 bits - [PCI_Reg: 78h] GPIO_69_68_66_65_Cntrl - RW 16 bits - [PCI_Reg: 7Eh] Page SmartPowerControl2A - RW 8 bits - [PCI_Reg: 98h] SmartPowerControl2B - RW 8 bits - [PCI_Reg: 99h] SmartPowerControl2C - RW 8 bits - [PCI_Reg: 9Ah] Page GPIO_12_to_4_Cntrl RW 32 bits - [PCI_Reg: A8h] SATA_Cntrl - RW 16 bits - [PCI_Reg: ACh] SATA_Cntrl - RW 16 bits - [PCI_Reg: ACh] MSI Mapping Capability - R - 32 bits - [PCI_Reg: B0h] PciIntGpio - RW - 16 bits - [PCI_Reg: BCh] UsbIntMap - RW - 16 bits - [PCI_Reg: BEh] UsbIntMap - RW - 16 bits - [PCI_Reg: BEh] IoDrvSth - RW - 32 bits - [PCI_Reg: C0h] Page Page Page Page AudioGpioControl RW - 32 bits - [Extend_Reg: 04h] Page Page Page Page Page Page Page Page Tmr1CntrlWord - RW 8 bits - [IO_Reg: 43h] Nmi_Status - RW 8 bits - [IO_Reg: 61h] Nmi_Enable - RW 8 bits - [IO_Reg: 70h] Page Page Page Page Page Page Page Page Page Register Name Offset Address Register Name Offset Address MiscControl - RW 8 bits - [PM_Reg: 00h] Page Page Page Page Programlo0RangeLo - RW 8 bits - [PM_Reg: 14h] ProgramIo0RangeHi - RW 8 bits - [PM_Reg: 15h] ProgramIo1RangeLo - RW 8 bits - [PM_Reg: 16h] Page Page Page Page GPMConfig0 RW 8 bits - [PM_Reg: 32h] GPMConfig1- RW 8 bits - [PM_Reg: 33h] GPMConfig2- RW 8 bits - [PM_Reg: 34h] GPMConfig3 RW 8 bits - [PM_Reg: 35h] GEvtLevelConfig - RW 8 bits - [PM_Reg: 36h] GPMLevelConfig0 - RW 8 bits - [PM_Reg: 37h] GPMLevelConfig1 - RW 8 bits - [PM_Reg: 38h] Page Page Page Page Page SmiSciSts2 - RW 8 bits - [PM_Reg: 5Ch] SmiSciSts3 - RW 8 bits - [PM_Reg: 5Dh] MwaitEnable - RW 8 bits - [PM_Reg: 5Eh] Page SwitchVoltageTime - RW 8 bits - [PM_Reg: 63h] SwitchGHI_Time - RW 8 bits - [PM_Reg: 64h] UsbPMControl- RW 8 bits - [PM_Reg: 65h] MiscEnable66 - RW 8 bits - [PM_Reg: 66h] MiscEnable67 RW 8 bits [PM_Reg:67h] Page Page Page Page Page Page Page Page Page Page Page Page Page Page 2.3.3.3 ACPI Registers Pm1Status - RW - 16 bits - [AcpiPmEvtBlk:00h] Pm1Enable - RW - 16 bits - [AcpiPmEvtBlk:02h] Page Page EVENT_STATUS - RW - 32 bits - [AcpiGpe0Blk:00h] EVENT_ENABLE - RW - 32 bits - [AcpiGpe0Blk:04h] SmiCmdPort - RW - 8 bits [SmiCmdBlk: 00h] SmiCmdStatus - RW - 8 bits [SmiCmdBlk: 01h] Page Page Page Page StatusMask0 RW - 8 bits - [ASF_IO: 0Bh] StatusMask1 RW - 8 bits - [ASF_IO: 0Ch] SlaveMisc- RW - 8 bits - [ASF_IO: 0Dh] Page 2.4 IDE Controller (Device 20, Function 1) 2.4.1 PCI Configuration Registers Vendor ID - R - 16 bits - [PCI_Reg:00h] Device ID - R - 16 bits - [PCI_Reg:02h] Device ID - R - 16 bits - [PCI_Reg:02h] Command - RW - 16 bits - [PCI_Reg:04h] Status - RW - 16 bits - [PCI_Reg:06h] Status - RW - 16 bits - [PCI_Reg:06h] Revision ID/Class Code- RW - 32 bits - [PCI_Reg:08h] Cache Line Size - RW - 8 bits - [PCI_Reg:0Ch] Page Page Interrupt Pin - R - 8 bits - [PCI_Reg:3Dh] Min_gnt - R - 8 bits - [PCI_Reg:3Eh] Max_latency - R - 8 bits - [PCI_Reg:3Fh] IDE PIO Timing - RW - 32 bits - [PCI_Reg:40h] Page Page IDE Internal Control - RW- 16 bits - [PCI_Reg:62h] IDE Misc. Control - RW- 32 bits - [PCI_Reg:64h] IDE MSI Programmable Weight - RW- 8 bits - [PCI_Reg:68h] IDE MSI Programmable Weight Register: This register specifies MSI weight. Page Page Page 2.5 AC 97 Controller Functional Descriptions Page Page Page Page UnMask Latency Timer Expiration W - 32 bits - [PCI_Reg: 50h] Interrupt - RW - 32 bits - [MEM_Reg: 00h] Interrupt Enable- RW - 32 bits - [MEM_Reg: 04h] Interrupt Enable- RW - 32 bits - [MEM_Reg: 04h] Audio Command- RW - 32 bits - [MEM_Reg: 08h] Audio Command- RW - 32 bits - [MEM_Reg: 08h] Phy Out Address and Data- RW - 32 bits - [MEM_Reg: 0Ch] Input Phy Address and Data- R - 32 bits - [MEM_Reg: 10h] Page Page Page Page Page Page Page CMD- RW - 16 bits - [PCI_Reg: 04h] STATUS- RW - 16 bits - [PCI_Reg: 06h] Revision ID/Class Code R - 32 bits - [PCI_Reg: 08h] Page Page Page Interrupt - RW - 32 bits - [MEM_Reg: 00h] Interrupt - RW - 32 bits - [MEM_Reg: 00h] Interrupt Enable - RW - 32 bits - [MEM_Reg: 04h] Modem Command - RW - 32 bits - [MEM_Reg: 08h] Page Modem Command - RW - 32 bits - [MEM_Reg: 08h] Phy Status and Address - RW - 32 bits - [MEM_Reg: 0Ch] Input Phy Address and Data - R - 32 bits - [MEM_Reg: 10h] Input Ch2 GPIO Data - R - 32 bits - [MEM_Reg: 14h] Page Page Page Page Page 2.6 HD Audio Controllers Registers Page Page Page Page Page Page Global Capabilities R 16 bits - [Mem_Reg: Base + 00h] Minor Version R 8 bits - [Mem_Reg: Base + 02h] Major Version R 8 bits - [Mem_Reg: Base + 03h] Page Wake Enable RW 16 bits - [Mem_Reg: Base + 0Ch] State Change Status RW 16 bits - [Mem_Reg: Base + 0Eh] Global Status RW 16 bits - [Mem_Reg: Base + 10h] Output Stream Payload Capability R 16 bits - [Mem_Reg: Base + 18h] Page Interrupt Status RW 32 bits - [Mem_Reg: Base + 24h] Wall Clock Counter R 32 bits - [Mem_Reg: Base + 30h] Stream Synchronization RW 32 bits [Mem_Reg: Base + 38h] CORB Lower Base Address RW 32 bits [Mem_Reg: Base + 40h] CORB Upper Base Address RW 32 bits [Mem_Reg: Base + 44h] CORB Write Pointer RW 16 bits [Mem_Reg: Base + 48h] CORB Read Pointer RW 16 bits [Mem_Reg: Base + 4Ah] CORB Control RW 8 bits [Mem_Reg: Base + 4Ch] Page RIRB Response Interrupt Count RW 16 bits [Mem_Reg: Base + 5Ah] RIRB Control RW 8 bits [Mem_Reg: Base + 5Ch] RIRB Status RW 8 bits [Mem_Reg: Base + 5Dh] RIRB Size RW 8 bits [Mem_Reg: Base + 5Eh] Immediate Command Output Interface RW 32 bits [Mem_Reg: Base + 60h] Immediate Command Input Interface RW 32 bits [Mem_Reg: Base + 64h] Immediate Command Input Interface RW 16 bits [Mem_Reg: Base + 68h] DMA Position Lower Base Address RW 32 bits [Mem_Reg: Base + 70h] Page Page Page Page Page Page 3 Register Descriptions: PCI Bridges 3.1 LPC ISA Bridge (Device 20, Function 3) LPC AMD SB600 Register Reference Manual Proprietary Page 250 PCI function 3 configuration registers are described below. VID- R - 16 bits - [PCI_Reg: 00h] DID- R - 16 bits - [PCI_Reg: 02h] CMD- RW - 16 bits - [PCI_Reg: 04h] AMD SB600 Register Reference Manual Proprietary Page 251 CMD- RW - 16 bits - [PCI_Reg: 04h] STATUS- RW - 16 bits - [PCI_Reg: 06h] Revision ID/Class Code - R - 8 bits - [PCI_Reg: 08h] Page AMD SB600 Register Reference Manual Proprietary Page 253 IO Port Decode Enable Register 1- RW - 8 bits - [PCI_Reg: 44h] IO Port Decode Enable Register 2- RW - 8 bits - [PCI_Reg: 45h] IO Port Decode Enable Register 3- RW - 8 bits - [PCI_Reg: 46h] IO Port Decode Enable Register 4- RW - 8 bits - [PCI_Reg: 47h] Page Page AMD SB600 Register Reference Manual Proprietary Page 256 LPC ROM Address Range 1 (Start Address) - RW - 16 bits - [PCI_Reg: 68h] LPC ROM Address Range 1 (End Address) - RW - 16 bits - [PCI_Reg: 6Ah] LPC ROM Address Range 2 (Start Address)- RW - 16 bits - [PCI_Reg: 6Ch] LPC ROM Address Range 2 (End Address) - RW - 16 bits - [PCI_Reg: 6Eh] AMD SB600 Register Reference Manual Proprietary Page 257 Firmware Hub Select RW* - 32 bits - [PCI_Reg: 70h] Alternative Wide IO Range Enable- RW - 32 bits - [PCI_Reg: 74h] Miscellaneous Control Bits- RW - 8 bits - [PCI_Reg: 78h] AMD SB600 Register Reference Manual Proprietary Page 258 Miscellaneous Control Bits- RW - 8 bits - [PCI_Reg: 78h] TPM (trusted plant form module) register- RW - 32 bits - [PCI_Reg: 7Ch] MSI Capability Register- R - 32 bits - [PCI_Reg: 80h] Page Page AMD SB600 Register Reference Manual Proprietary Page 261 SPI_Cntrl0 Register- RW - 32 bits - [Mem_Reg 00h] SPI_RestrictedCmd1 Register- RW - 32 bits - [Mem_Reg 04h] SPI_RestrictedCmd2 Register- RW - 32 bits - [Mem_Reg 08h] AMD SB600 Register Reference Manual Proprietary Page 262 SPI_RestrictedCmd2 Register- RW - 32 bits - [Mem_Reg 08h] SPI_Cntrl1 Register- RW - 32 bits - [Mem_Reg 0Ch] SPI_CmdValue0 Register- RW - 32 bits - [Mem_Reg 10h] Page Page 3.2 Host PCI Bridge Registers (Device 20, Function 4) PCI Vender ID - R - 16 bits - [PCI_Reg: 00h] Device ID - R - 16 bits - [PCI_Reg: 02h] Command - RW - 16 bits - [PCI_Reg: 04h] Status- RW - 16 bits - [PCI_Reg: 06h] Page Page Page IO Limit Upper 16 bits- RW - 16 bits - [PCI_Reg: 32h] Capabilities Pointer- R - 8 bits - [PCI_Reg: 34h] Interrupt Line- R - 8 bits - [PCI_Reg: 3Ch] Interrupt Pin- R - 8 bits - [PCI_Reg: 3Dh] Bridge Control- RW - 16 bits - [PCI_Reg: 3Eh] Bridge Control- RW - 16 bits - [PCI_Reg: 3Eh] CPCTRL- RW - 8 bits - [PCI_Reg: 40h] DCTRL- RW - 8 bits - [PCI_Reg: 41h] Page PCICLK Enable Bits- RW - 8 bits - [PCI_Reg: 4Ah] Misc Control RW - 8 bits - [PCI_Reg: 4Bh] AutoClockRun control RW - 32 bits - [PCI_Reg: 4Ch] Dual Address Cycle Enable and PCIB_CLK_Stop Override - RW - 16 bits - [PCI_Reg: 50h] Dual Address Cycle Enable and PCIB_CLK_Stop Override - RW - 16 bits - [PCI_Reg: 50h] MSI Mapping Capability R - 32 bits - [PCI_Reg: 54h] - R - 32 bits - [PCI_Reg: 58h] Prefetch Timeout Limit - 16 bits - [PCI_Reg: 5Ch] Prefetch Size Control - 32 bits - [PCI_Reg: 60h] Misc Control Register - 32 bits - [PCI_Reg: 64h] Misc Control Register - 32 bits - [PCI_Reg: 64h] AMD SB600 Register Reference Manual Proprietary Page 277 4 Register Descriptions: General Purpose Functions/Interrupt Controllers/Support Function Pins 4.1 GPIO/GPOC Page Page Page Page Page 4.2 GEVENT/GPE/GPM/ExtEvent Page Page AMD SB600 Register Reference Manual Proprietary Page 286 Page 4.3 THRMTRIP/TALERT 4.4 Real Time Clock (RTC) RTC Page Page Page Register A - RW 8 bits - [RTC_Reg: 0Ah] Rate Selection Bits RS3 RS2 RS1 RS0 Tap Frequency(Interrupt Rate) Register B - RW 8 bits - [RTC_Reg: 0Bh] Register C - R 8 bits - [RTC_Reg: 0Ch] Page Page 4.5 IOXAPIC Registers Page Page Appendix A: AC97 Audio FAQs Appendix B: Revision History