Field Name Bits Default Description
Port Change
Detect
2 0b Port Change Detect. The Host Controller sets this bit to a one when any
port for which the Port Owner bit is set to zero (see Section 2.3.9) has a
change bit transition from a zero to a one or a Force Port Resume bit
transition from a zero to a one as a result of a J-K transition detected on a
suspended port. This bit will also be set as a result of the Connect Status
Change being set to a one after system software has relinquished
ownership of a connected port by writing a zero to a port's Port Owner bit.
This bit is allowed to be maintained in the Auxiliary power well.
Alternatively, it is also acceptable that on a D3 to D0 transition of the
EHCI HC device, this bit is loaded with the OR of all of the PORTSC
change bits (including: Force port resume, over-current change,
enable/disable change and connect status change).
Frame List
Rollover
3 0b Frame List Rollover. The Host Controller sets this bit to a one when the
Frame List Index rolls over from its maximum value to zero. The exact
value at which the rollover occurs depends on the frame list size. For
example, if the frame list size (as programmed in the Frame List Size field
of the USBCMD register) is 1024, the Frame Index Register rolls over
every time FRINDEX[13] toggles. Similarly, if the size is 512, the Host
Controller sets this bit to a one every time FRINDEX[12] toggles.
Host System Error 4 0b Host System Error. The Host Controller sets this bit to 1 when a serious
error occurs during a host system access involving the Host Controller
module. In a PCI system, conditions that set this bit to 1 include PCI
Parity error, PCI Master Abort, and PCI Target Abort. When this error
occurs, the Host Controller clears the Run/Stop bit in the Command
register to prevent further execution of the scheduled TDs.
Interrupt on Async
Advance
5 0b Interrupt on Async Advance. System software can force the host
controller to issue an interrupt the next time the host controller advances
the asynchronous schedule by writing a one to the Interrupt on Async
Advance Doorbell bit in the USBCMD register. This status bit indicates the
assertion of that interrupt source.
Reserved 11:6 These bits are reserved and should be set to zero.
HCHalted 12 1b HCHalted. This bit is a zero whenever the Run/Stop bit is a one. The Host
Controller sets this bit to one after it has stopped executing as a result of
the Run/Stop bit being set to 0, either by software or by the Host
Controller hardware (e.g. internal error). [Read-only]
Reclamation 13 0b Reclamation. This is a read-only status bit, which is used to detect an
empty asynchronous schedule. [Read-only]
Periodic Schedule
Status
14 0b Periodic Schedule Status. The bit reports the current real status of the
Periodic Schedule. If this bit is a zero then the status of the Periodic
Schedule is disabled. If this bit is a one then the status of the Periodic
Schedule is enabled. The Host Controller is not required to immediately
disable or enable the Periodic Schedule when software transitions the
Periodic Schedule Enable bit in the USBCMD register. When this bit and
the Periodic Schedule Enable bit are the same value, the Periodic
Schedule is either enabled (1) or disabled (0). [Read-only]
Asynchronous
Schedule Status
15 0b Asynchronous Schedule Status. The bit reports the current real status of
the Asynchronous Schedule. If this bit is a zero then the status of the
Asynchronous Schedule is disabled. If this bit is a one then the status of
the Asynchronous Schedule is enabled. The Host Controller is not
required to immediately disable or enable the Asynchronous Schedule
when software transitions the Asynchronous Schedule Enable bit in the
USBCMD register. When this bit and the Asynchronous Schedule Enable
bit are the same value, the Asynchronous Schedule is either enabled (1)
or disabled (0). [Read-only]
Reserved 31:16 These bits are reserved and should be set to zero.