AMD SB600 AMD SB600 Register Reference Manual Proprietary Page 258 , Miscellaneous Control Bits- RW - 8 bits - [PCI_Reg: 78h] , TPM (trusted plant form module) register- RW - 32 bits - [PCI_Reg: 7Ch] , MSI Capability Register- R - 32 bits

AMD SB600 Register Reference Manual Proprietary Page 258 Miscellaneous Control Bits- RW - 8 bits - [PCI_Reg: 78h]

Field Name Bits Default Description

Msi On 1 0b When this bit is set to 1, it turns on LPC MSI capability. The

following will be true:

* Reg0x04[20] (capabilities list) reads 1.

* Reg0x34[7:0] (capabilities pointer) reads 80h

When this bit is set to 0, it turns off lpc MSI capability. The

following will be true:

* Reg0x04[20] reads 0.

* Reg0x34[7:0] reads 0.

Reserved 31:2 0000_0000h

TPM (trusted plant form module) register- RW - 32 bits - [PCI_Reg: 7Ch]

Field Name Bits Default Description

Tpm12_en 0 0b When set to 1, it enables decoding of tpm (trusted platform

module) cycles defined in TPM1.2 spec (Refer to the

addresses defined in bit[1] below). Note that tpm12_en and

tpm_legacy are independent bits; they respectively turn on

decoding of different tpm addresses.

Tpm_amd 1 0b This bit is replaced with strap pin K8system (to support AMD

K8 CPU), and no longer in use. It is read only and returns 0.

When the strap is 0, it ONLY supports these normal tpm

cycles. Here are the cycle definition. (Left hand side is

system/software memory address, which is translated to LPC

IO address on the right hand side.)

0xFED4_0xxx --> 0x0xxx

0xFED4_1xxx --> 0x1xxx

0xFED4_2xxx --> 0x2xxx

0xFED4_3xxx --> 0x3xxx

0xFED4_4xxx --> 0x4xxx

When the strap is 1, it ONLY supports these AMD tpm

cycles.

0xFED4_0xxx --> 0x0xxx

0xFED4_1xxx --> 0x1xxx

0xFED4_2xxx --> 0x2xxx

0xFED4_3xxx --> 0x3xxx

0xFD_F920_0000~0xFD_F923_FFFF --> 0x4028

0xFD_F928_0000~0xFD_F928_0003 --> 0x4020

0xFD_F928_0004~0xFD_F928_0007 -->

0x4024~0x4027

Tpm_legacy 2 0b When set to 1, it enables decoding of legacy tpm addresses,

i.e., IO addresses 7E/7F and EE/EF will be decoded.

Tmkbc_enable 3 0b Enab le bit for the TMKBC function

Tmkbc_set 4 0b Write once bit. Once set, all tmkbc address/remap registers

cannot be changed until the next reset.

Tmkbc_sel 6:5 0h There are actually four sets of TMKBC mapping registers.

These two bits select which one of four sets of tmkbc

registers at 84, 88, and 8Ch to be accessed.

Reserved 31:7 0000000h

Note: Any tpm cycle above is decoded only when the cycle is started by ALinkBridge. Access from bus master

devices is not allowed.

MSI Capability Register- R - 32 bits - [PCI_Reg: 80h]

Field Name Bits Default Description

CAP ID 7:0 08h CAP ID.

CAP Next Pointer 15:8 00h CAP Next Pointer.

CAP Enable 16 1b CAP Enable.