AMD SB600 AMD SB600 Register Reference Manual Proprietary Page 28 , HBA Capabilities R - 32bits [Mem_reg: ABAR + 00h] , Global HBA Control RW

AMD SB600 Register Reference Manual Proprietary Page 28 HBA Capabilities – R - 32bits [Mem_reg: ABAR + 00h]

Field Name Bits Default Description

Supports Native

Command Queuing

(SNCQ)

30 1b Indicates whether the HBA supports Serial ATA native

command queuing. If set to ‘1’, an HBA shall handle DMA

Setup FISes natively, and shall handle the auto-activate

optimization through that FIS. If cleared to ‘0’, native

command queuing is not supported and software should not

issue any native command queuing commands.

Supports 64-bit

Addressing (S64A)

31 1b Indicates whether the HBA can access 64-bit data structures.

When set to ‘1’, the HBA shall make the 32-bit upper bits of

the port DMA Descriptor, the PRD Base, and each PRD entry

read/write. When cleared to ‘0’, these are read-only and

treated as ‘0’ by the HBA.

Global HBA Control – RW - 32bits [Mem_reg: ABAR + 04h]

Field Name Bits Default Description

HBA Reset (HR) 0 0b When set by SW, this bit causes an internal reset of the HBA.

All state machines that relate to data transfers and queuing

shall return to an idle condition, and all ports shall be re-

initialized via COMRESET (if staggered spin-up is not

supported). If staggered spin-up is supported, then it is the

responsibility of software to spin-up each port after the reset

has completed.

When the HBA has performed the reset action, it shall reset

this bit to ‘0’. A software write of ‘0’ shall have no effect. For

a description on which bits are reset when this bit is set.

Interrupt Enable (IE) 1 0b This global bit enables interrupts from the HBA. When

cleared (reset default), all interrupt sources from all ports are

disabled. When set, interrupts are enabled.

MSI Revert to Single

Message (MRSM)

2 0b

Read Only

When set to ‘1’ by hardware, indicates that the HBA

requested more than one MSI vector but has reverted to

using the first vector only. When this bit is cleared to ‘0’, the

HBA has not reverted to single MSI mode (i.e. hardware is

already in single MSI mode, software has allocated the

number of messages requested, or hardware is sharing

interrupt vectors if MC.MME < MC.MMC).

The HBA may revert to single MSI mode when the number of

vectors allocated by the host is less than the number

requested. This bit shall only be set to ‘1’ when the following

conditions hold:

• MC.MSIE = ‘1’ (MSI is enabled)

• MC.MMC > 0 (multiple messages requested)

• MC.MME > 0 (more than one message allocated)

• MC.MME != MC.MMC (messages allocated not

equal to number requested)

When this bit is set to ‘1’, single MSI mode operation is in use

and software is responsible for clearing bits in the IS register

to clear interrupts.

This bit shall be cleared to ‘0’ by hardware when any of the

four conditions stated is false. This bit is also cleared to ‘0’

when MC.MSIE = ‘1’ and MC.MME = 0h. In this case, the

hardware has been programmed to use single MSI mode,

and is not “reverting” to that mode.

Reserved 30:3 Reserved.