AMD SB600 AMD SB600 Register Reference Manual Proprietary Page 34 , Port-N Interrupt Enable - RW -32 bits [Mem_reg: ABAR + port offset + 14h] , Port-N Command and Status - R - 32 bits [Mem

AMD SB600 Register Reference Manual Proprietary Page 34 Port-N Interrupt Enable - RW -32 bits [Mem_reg: ABAR + port offset + 14h]

Field Name Bits Default Description

Cold Presence Detect

Enable (CPDE)

31 0b

When set, GHC.IE is set, and P0S.CPDS is set, the HBA

shall generate an interrupt.

For systems that do not support cold presence detect, this bit

shall be a read-only ‘0’.

Port-N Command and Status - R - 32 bits [Mem_reg: ABAR + port offset + 18h]

Field Name Bits Default Description

Start (ST) 0 0b RW

When set, the HBA may process the command list. When

cleared, the HBA may not process the command list.

Whenever this bit is changed from a ‘0’ to a ‘1’, the HBA

starts processing the command list at entry ‘0’. Whenever

this bit is changed from a ‘1’ to a ‘0’, the PxCI register is

cleared by the HBA upon the HBA putting the controller into

an idle state. This bit shall only be set to ‘1’ by software after

PxCMD.FRE has been set to ‘1’.

Spin-Up Device (SUD) 1 1b This bit is read/write for HBAs that support staggered spin-up

via CAP.SSS. This bit is read only ‘1’ for HBAs that do not

support staggered spin-up. On an edge detect from ‘0’ to ‘1’,

the HBA shall start a COMRESET initialization sequence to

the device. Clearing this bit to ‘0’ does not cause any OOB

signal to be sent on the interface. When this bit is cleared to

‘0’ and PxSCTL.DET=0h, the HBA will enter listen mode.

Power On Device (POD) 2 1b T his bit is read/write for HBAs that support cold presence

detection on this port as indicated by PxCMD.CPD set to ‘1’.

This bit is read only ‘1’ for HBAs that do not support cold

presence detect. When set, the HBA sets the state of a pin

on the HBA to ‘1’ so that it may be used to provide power to a

cold-presence detectable port.

Command List Override

(CLO)

3 0b

Setting this bit to ‘1’ causes PxTFD.STS.BSY and

PxTFD.STS.DRQ to be cleared to ‘0’. This allows a software

reset to be transmitted to the device regardless of whether

the BSY and DRQ bits are still set in the PxTFD.STS register.

The HBA sets this bit to ‘0’ when PxTFD.STS.BSY and

PxTFD.STS.DRQ have been cleared to ‘0’. A write to this

This bit shall only be set to ‘1’ immediately prior to setting the

PxCMD.ST bit to ‘1’ from a previous value of ‘0’. Setting this

bit to ‘1’ at any other time is not supported and will result in

indeterminate behavior. Software must wait for CLO to be

cleared to ‘0’ before setting PxCMD.ST to ‘1’.

FIS Receive Enable

(FRE)

4 0b

When set, the HBA may post received FISes into the FIS

receive area pointed to by PxFB (and for 64-bit HBAs,

PxFBU). When cleared, received FISes are not accepted by

the HBA, except for the first D2H register FIS after the

initialization sequence, and no FISes are posted to the FIS

receive area.

System software must not set this bit until PxFB (PxFBU)

have been programmed with a valid pointer to the FIS receive

area, and if software wishes to move the base, this bit must

first be cleared, and software must wait for the FR bit in this

Reserved 7:5 Reserved