©2008 Advanced Micro Devices, Inc. Features of the SB600
AMD SB600 Register Reference Manual Proprietary Page 9
1.3 Features of the SB600
CPU Interface
Supports both Single and Dual core AMD
CPUs
Desktop: Athlon 64, Athlon 64 FX, Athlon
64 X2, Sempron, Opteron, dual-core
Opteron
Mobile: Athlon XP-M, Mobile Athlon 64,
Turion 64, Mobile Sempron
PCI Host Bus Controller
Supports PCI Rev. 2.3 specification
Supports PCI bus at 33MHz
Supports up to 6 bus master devices
Supports 40-bit addressing
Supports interrupt steering for plug-n-play
devices
Supports concurrent PCI operations
Supports hiding of PCI devices by
BIOS/hardware
Supports spread spectrum on PCI clocks
USB controllers
5 OHCI and 1 EHCI Host controllers to
support 10 USB ports
All 10 ports are USB 1.1 (“Low Speed”, “Full
Speed”) and 2.0 (“High Speed”) compatible
Supports ACPI S1~S5
Supports legacy keyboard/mouse
Supports USB debug port
Supports port disable with individual control
SMBus Controller
SMBus Rev. 2.0 compliant
Support SMBALERT # signal / GPIO
Interrupt Controller
Supports IOAPIC/X-IO APIC mode for 24
channels of interrupts
Supports 8259 legacy mode for 15 interrupts
Supports programmable level/edge triggering
on each channels
Supports serial interrupt on quiet and
continuous modes
DMA Controller
Two cascaded 8237 DMA controllers
Supports PC/PCI DMA
Supports LPC DMA
Supports type F DMA
LPC host bus controller
Supports LPC based super I/O and flash
devices
Supports two master/DMA devices
Supports TPM version 1.1/1.2 devices for
enhanced security
Supports SPI devices
SATA II AHCI Controller
Supports four SATA ports, complying with the
SATA 2.0 specification
Supports SATA II 3.0GHz PHY, with
backward compatibility with 1.5GHz
Supports RAID striping (RAID 0) across all 4
ports
Supports RAID mirroring (RAID 1) across all 4
ports
Supports RAID 10 (4 ports needed)
Supports both AHCI mode and IDE mode
Supports advanced power management with
ACHI mode
IDE Controller
Single PATA channel support
Supports PIO, Multi-word DMA, and Ultra
DMA 33/66/100/133 modes
32x32byte buffers on each channel for
buffering
Swap bay support by tri-state IDE signals
Supports Message Signaled Interrupt (MSI)
Integrated IDE series resistors