©2008 Advanced Micro Devices, Inc. SMBus Module and ACPI Block (Device 20, Function 0)
AMD SB600 Register Reference Manual Proprietary Page 96
2.3 SMBus Module and ACPI Block (Device 20, Function 0)
Some registers in the SMBus/ACPI PCI configuration space (PCI_reg, see section 2.3.1) contain controls
and settings for a number of blocks within the SB600. Figure 4 below shows these blocks, with their affected
functions and the associated PCI_reg registers.
USB
OHCI / EHCI Controller Enables
USB Reset / PowerDown
USB Legacy control
USB Smart Power Control
USB PM & SMI Control
AD:AC
10h
08h --
Bus 0 Dev 20 Function 0
SATA
SATA Enables
SATA power saving
SATA Interrupt Map register
SATA Smart Power Control
AC/AFh
5Ch 98h
PCI_Reg:
64/68/6Bh
5Ch 98h
PCI_Reg:
PCI
PCI Stop Clock enable
PCI Bridge Soft Reset Enable
PCI Bus drive strength registers
RTC
RTC Ram Protection
External RTC Enable
RTC I/O Addr Enable
64h
6Ah 78h
PCI_Reg:
C0h
6Ch 64h
PCI_Reg:
Keyboard Control
Keyboard Reset
Keyboard Interrupt IRQ 12 filter
External keyboard reset enable
Mouse control
Serirq controller registers
PIC / IOAPIC
PIC /IOAPIC Enable
IOAPIC Base Address
IOAPIC clock control
64h
62h 69h
PCI_Reg: 74h
64h
PCI_Reg:
GPIO
GPIO Enables
GPIO Status
Gpio input / output registers
SMBus / I2C
I2C port enables
I2C port Address register
I2C port R/W shadow port
I2C bus revision ID
Smbus base Address
SATA SMBus control
AD:AC h
D5:D2 h 90 h
PCI_Reg:
PCI_Reg:
--
BC h --
81:80 h
58:50 h A0:AC h
PCI_Reg:
AD:AC
74h
F0h --
I/O PORTS
I/O Port Address enables
I/O C50 -C52 Enable
PM I/O register CD6 / CD7 Enable
Base Addr I/O or Mem map control
K8 I/O Wake Address
Memory Window
ISA Address Decode registers
ROM Address enables
--
78h F4h
PCI_Reg: 41h
49:48 h --
PCI_Reg:
LPC
LPC Controller Enable
LPC Drive strength control
Misc
K8 Intr Enable
MSI Mapping register
Ext Gate A20
AB register base address
Multimedia timer enable
8250 Timer Eenable
PCI-SPCI clock ratio
B0/E0 h
62h 64h
PCI_Reg:
C0h
64h --
PCI_Reg: