Field Name Bits Default HCD HC Description
RD 3 0b RW W 0 - Ignore
1 - Enable interrupt generation due to Resume
Detect.
UE 4 0b RW RW 0 - Ignore
1 - Enable interrupt generation due to Unrecoverable
Error.
FNO 5 0b RW RW 0 - Ignore
1 - Enable interrupt generation due to Frame Number
Overflow.
RHSC 6 0b RW RW 0 - Ignore
1 - Enable interrupt generation due to Root Hub
Status Change.
Reserved 29:7 Reserved
OC 30 0b RW RW 0 - Ignore
1 - Enable interrupt generation due to Ownership
Change.
MIE 31 0b RW R A ‘0’ written to this field is ignored by HC. A '1' written
to this field enables interrupt generation due to events
specified in the other bits of this register. This is used
by HCD as a Master Interrupt Enable.
HcInterruptDisable - 32 bits - [MEM_Reg : 14h] Field Name Bits Default HCD HC Description
SO 0 0b RW R 0 - Ignore
1 - Disable interrupt generation due to Scheduling
Overrun.
WDH 1 0b RW R 0 - Ignore
1 - Disable interrupt generation due to HcDoneHead
Writeback.
SF 2 0b RW R 0 - Ignore
1 - Disable interrupt generation due to Start of Frame.
RD 3 0b RW R 0 - Ignore
1 - Disable interrupt generation due to Resume
Detect.
UE 4 0b RW R 0 - Ignore
1 - Disable interrupt generation due to Unrecoverable
Error.
FNO 5 0b RW R 0 - Ignore
1 - Disable interrupt generation due to Frame Number
Overflow.
RHSC 6 0b RW R 0 - Ignore
1 - Disable interrupt generation due to Root Hub
Status Change.
Reserved 29:7 Reserved
OC 30 0b RW R 0 - Ignore
1 - Disable interrupt generation due to Ownership
Change.
MIE 31 0b RW R A '0' written to this field is ignored by HC. A '1' written
to this field disables interrupt generation due to
events specified in the other bits of this register. This
field is set after a hardware or software reset.
HcHCCA - 32 bits - [MEM_Reg : 18h] Field Name Bits Default HCD HC Description
Reserved 7:0 Reserved
HCCA 31:8 000000h RW R This is the base address of the Host Controller
Communication Area