Field Name Bits Default Description
Interrupt Line 7:0 00h T he Interrupt Line is a field used to communicate interrupt
line routing information. The register is read/write and must
be implemented by any device (or device function) that uses
an interrupt pin. POST software will write the routing
information into this register as it initializes and configures
the system.
The value in this field tells which input of the system
interrupt controller(s) the device's interrupt pin is connected
to. The device itself does not use this value; rather it is used
by device drivers and operating systems. Device drivers
and operating systems can use this information to determine
priority and vector information. Values in this register are
system architecture specific.
Interrupt Pin 15:8 04h
Read Only by default.
Hard-wired to 04h, which corresponds to using INTD#.
MIN_GNT 23:16 00h Read Only. Hard-wired to 00h to indicate no major
requirements for the settings of Latency Timers.
MAX_LAT 31:24 00h Read Only. Hard-wired to 00h to indicate no major
requirements for the settings of Latency Timers.
Field Name Bits Default Description
Reserved 4:0 00h Reserved
PME Disable 5 0b Set to 1 to disable EHCI PME support
MSI Disable 6 0b Set to 1 to disable EHCI MSI support
Reserved 15:7 000h Reserved
Cache Timer Control 19:16 Eh Control the purge timeout timer if HC doesn't come back to
request the data.
Counter Max Time (ns) Min Time (ns)
0 45 30
1 90 60
2 180 120
3 360 240
4 720 480
5 1440 960
6 2880 1920
7 5760 3840
8 11520 7680
9 23040 15360
A 46080 30720
B 92160 61440
C 184320 122880
D 368640 245760
E 737280 491520
F No limit
Cache Prefetch Disable 20 0b 0: Enable EHCI cache prefetch.
1: Disable EHCI cache prefetch.
Reserved 23:21
Disable Async QH Cache
on IN xfer
24 0b Set to 1 to disable async QH/QTD cache during IN xfer.