AMD SB600 - page 233

©2008 Advanced Micro Devices, Inc. HD Audio Controllers Registers
AMD SB600 Register Reference Manual Proprietary Page 233
Register Name Address Offset
Immediate Command Input Interface 64h
Immediate Command Input Interface 68h
DMA Position Buffer Lower Base Address 70h
DMA Position Buffer Upper Base Address 74h
Control 80h
Status 83h
Link Position in Current Buffer 84h
Cyclic Buffer Length 88h
Last Valid Index 8Ch
FIFO Size 90h
Stream Format 92h
Buffer Descriptor Lower Base Address 98h
Buffer Descriptor Upper Base Address 9Ch
Control A0h
Status A3h
Link Position in Current Buffer A4h
Cyclic Buffer Length A8h
Last Valid Index ACh
FIFO Size B0h
Stream Format B2h
Buffer Descriptor Lower Base Address B8h
Buffer Descriptor Upper Base Address BCh
Control C0h
Status C3h
Link Position in Current Buffer C4h
Cyclic Buffer Length C8h
Last Valid Index CCh
FIFO Size D0h
Stream Format D2h
Buffer Descriptor Lower Base Address D8h
Buffer Descriptor Upper Base Address DCh
Control E0h
Status E3h
Link Position in Current Buffer E4h
Cyclic Buffer Length E8h
Last Valid Index ECh
FIFO Size F0h
Stream Format F2h
Buffer Descriptor Lower Base Address F8h
Buffer Descriptor Upper Base Address FCh
Control 100h
Status 103h
Link Position in Current Buffer 104h
Cyclic Buffer Length 108h
Last Valid Index 10Ch
FIFO Size 110h
Stream Format 112h
Buffer Descriptor Lower Base Address 118h
Buffer Descriptor Upper Base Address 11Ch
Control 120h
Status 123h
Link Position in Current Buffer 124h
Cyclic Buffer Length 128h
Last Valid Index 12Ch
FIFO Size 130h
Stream Format 132h
Buffer Descriptor Lower Base Address 138h
Buffer Descriptor Upper Base Address 13Ch