AMD SB600 - page 66

AMD SB600 Register Reference Manual Proprietary Page 66

HcRhPortStatus - 32 bits - [MEM_Reg : 50h+4*(1:NDP)]

Field Name Bits Default HCD HC Description

CSC 16 0b RW RW

ConnectStatusChange

This bit is set whenever a connect or disconnect

event occurs. The HCD writes a ‘1’ to clear this bit.

Writing a ‘0’ has no effect. If CurrentConnectStatus

is cleared when a SetPortReset, SetPortEnable, or

SetPortSuspend write occurs, this bit is set to force

the driver to re-evaluate the connection status since

these writes should not occur if the port is

disconnected.

0 = No change in CurrentConnectStatus

1 = Change in CurrentConnectStatus

Note: If the DeviceRemovable[NDP] bit is set, this

bit is set only after a Root Hub reset to inform the

system that the device is attached.

PESC 17 0b RW RW

PortEnableStatusChange

This bit is set when hardware events cause the

PortEnableStatus bit to be cleared. Changes from

HCD writes do not set this bit. The HCD writes a ‘1’ to

clear this bit. Writing a ‘0’ has no effect.

0 = No change in PortEnableStatus

1 = Change in PortEnableStatus

PSSC 18 0b RW RW

PortSuspendStatusChange

This bit is set when the full resume sequence has

been completed. This sequence includes the 20-s

resume pulse, LS EOP, and 3-ms resychronization

delay. The HCD writes a ‘1’ to clear this bit. Writing a

‘0’ has no effect. This bit is also cleared when

ResetStatusChange is set.

0 = Resume is not completed

1 = Resume completed

OCIC 19 0b RW RW

PortOverCurrentIndicatorChange

This bit is valid only if overcurrent conditions are

reported on a per-port basis. This bit is set when Root

Hub changes the PortOverCurrentIndicator bit. The

HCD writes a ‘1’ to clear this bit. Writing a ‘0’ has no

effect.

0 = No change in PortOverCurrentIndicator

1 = PortOverCurrentIndicator has changed

PRSC 20 0b RW RW

PortResetStatusChange

This bit is set at the end of the 10-ms port reset

signal.

The HCD writes a ‘1’ to clear this bit. Writing a ‘0’ has

no effect.

0 = Port reset is not complete

1 = Port reset is complete

Reserved 31:21 Reserved

2.2.2 USB Legacy Keyboard Operation

2.2.2.1 Overview

To support applications and drivers in non-USB-aware environments (e.g., DOS), the Host Controller needs

to provide some amount of hardware support for the emulation of a PS/2 keyboard and/or mouse by their

USB equivalents. For Open HCI, this emulation support is provided by a set of registers that are controlled

by code running in SMM. Working in conjunction, this hardware and software produces approximately the

same behavior-to-application code as would be produced by a PS/2-compatible keyboard and/or mouse

interface.

To minimize hardware impact, the Host Controller accesses a USB keyboard and/or mouse using the