14
K
A
DAK
General AMX Operation
The Interrupt Supervisor
Tasks execute with the processor interrupt facility enabled to permit service of external
devices. When an external interrupt occurs, the task is interrupted in the m anner dictat ed
by the processor. The processor automatically saves the return address and some subset
of the processor state (registers, flags, etc.) and branches to an Interrupt Service
Procedure (ISP). The exact vectoring method is determined by the hardware
configuration employed in the system.
Two types of ISPs exist: nonconforming ISPs and conforming ISPs.
A nonconforming ISP must quickly service the device to remove the interrupting
condition. The ISP must preserve all registers which it uses. The nonconforming ISP
cannot make calls to any AMX service procedures.
A conforming ISP can make use of a subset of the AMX service procedures. A
conforming ISP consists of an ISP root and an Interrupt Handler. The processor vectors
to the ISP root which informs the AMX Interrupt Supervisor that the interrupt has
occurred. The Interrupt Supervisor preserves the state of the interrupted task and, if
necessary, switches to an interrupt stack. The Interrupt Supervisor then calls the
associated Interrupt Handler.
The Interrupt Handler must quickly service the device to remove the interrupting
condition. The handler is free to make procedure calls to a subset of the AMX service
facilities. When device service is completed, the AMX Interrupt Supervisor dismisses
the interrupt.
The AMX Interrupt Supervisor monitors calls made by the Interrupt Handler to AMX
service procedures. If no such calls have been made, AMX automatically restores the
state of the interrupted task and returns directly to the interrupted task at its point of
interruption.
The Interrupt Handler may have requested AMX to initiate or resume execution of some
task of higher priority than the interrupted task. If so, the AMX Interrupt Supervisor
suspends the interrupted task and marks it as ready to resume execution at the earliest
opportunity. The AMX Task Scheduler is then invoked to determine the highest priority
task capable of execution.
The AMX Interrupt Supervisor supports nested interrupts on processors which provide
this capability. If interrupts nest, the Interrupt Supervisor defers its task switching checks
until all of the concurrent interrupts have been serviced.
Note
A conforming ISP root can be created using AMX
procedure ajispm.