Interrupt Service Procedures
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The AMX Interrupt Supervisor, when invoked, switches to an Interrupt Stack provided
by you in your System Configuration Module. The AMX Interrupt Supervisor then
returns to the application ISP. The ISP must perform all services required by the device.
Upon return to the ISP from the AMX Interrupt Supervisor entry procedure AAINT, the
registers are initialized as follows.
Interrupts are disabled.
All registers are free for use.
DS,ES DGROUP Segment
SS:SP AMX Interrupt Stack ready for use
CX,DX,SI Unaltered by procedure AAINT
The direction flag is set to forward.
All other registers are undefined.
It should be noted that AMX procedure AAINT preserves registers CX, DX and SI. This
feature can be used to advantage when creating special ISPs like those described in
Chapter 4.7.
The external interrupt facility is disabled. Your ISP can enable the external interrupt
facility if so desired. In this case, the ISP must be sure to either clear the source of the
interrupt before enabling interrupts or to mask (disable) the interrupt source if the
hardware exists to do so.
When the interrupt service is complete, the ISP informs the AMX Interrupt Supervisor by
issuing the termination call to AAINX. The final IRET instruction restores the processor
flags register and returns to the point of interruption.
It is important to note that, because of task switching invoked by AAINX, there may be a
significant delay before AMX returns to your IRET to resume execution of the interrupted
task. No device operations, AMX calls or commands to an interrupt controller such as
the Intel 8259 chip are allowed after the call to AAINX.