ASIC Driver Commands on Cisco IOS XR Software
show controllers plim asic
SPI4 AFull 0 | (0x3e80) | ||
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SPI4 AFull 1 | (0x4b00) | ||
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Buffer Full | (0x5780) | ||
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Buffer End | (0x63ff) |
Table 15 describes the significant fields shown in the display.
Table 15 | show controllers plim asic | |
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Field |
| Description |
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Ifname |
| Identifies the primary transmit interface. |
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SPI4.2 Channel state | Indicates if the SPI4.21 channel is provisioned. | |
Bay number |
| Identifies the bay that hosts the specified SPI4.2 receive channel. |
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| Can be 0 or 1. |
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Rx SPI4.2 channel number | Identifies the SPI4.2 receive channel whose information is | |
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| displayed. |
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Internal Buffer number | Identifies the internal buffer associated with the SPI4.2 receive | |
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| channel. |
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Rx edram buffer start address | Embedded DRAM buffer start address in hexadecimal format. | |
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Rx edram buffer end address | Embedded DRAM buffer end address in hexadecimal format. | |
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Rx edram buffer size | Embedded DRAM buffer size in hexadecimal format. | |
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Rx length buffer start address | Receive length buffer start address in hexadecimal format. | |
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Rx length buffer end address | Receive length DRAM buffer end address in hexadecimal format. | |
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Rx length buffer size | Receive length DRAM buffer size in hexadecimal format. | |
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Number of calendar entries | Number of entries in the SPI4.2 calendar. | |
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Quantum |
| Average number of bytes in the interface queue. |
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Buffer Almost Full Threshold | An increment counter which indicates that the transmit buffer is | |
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| almost full. The “Buffer Almost Full Threshold” is expressed in |
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| hexadecimal format. |
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Tx Queuing ASIC port number | Identifies the SPI4.2 transmit port. | |
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RxEDRAM buffer threshold | Displays embedded DRAM receive buffer threshold counter | |
settings |
| settings in hexadecimal format. |
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1. System Packet Level Interface 4.2
| Cisco IOS XR Advanced System Command Reference |
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