ASIC Driver Commands on Cisco IOS XR Software
show controllers cpuctrl cdma channel
AR-42
Cisco IOS XR Advanced System Command Reference
OL-14340-01
Tabl e 1 describes the significant fields shown in the display.
Table1 show controllers cpuctrl cdma channel Field Descriptions
Field Description
DMA queue Identifies the DMA1 queue.
Channel Identifies the channel whose DMA queue is displayed. 0 is the
ingress channel, and 1 is the egress channel
queue Identifies the queue.
state Current state of the queue.
OS Interrupt Level Current interrupt level for the queue.
Cpuctrl Interrupt Level Current interrupt level for the CPU controller.
OS Run Priority Run priority level for this queue.
client handle Internal identifier for the Cisco client.
ISR context Internal information about the location of the ISR2 pointer.
Pakman/Bufman Instance Internal information about the location of the Pakman and Bufman
Instance.
client callback function pointer Internal information about the client callback function pointer.
cleanup function Internal information about the client cleanup function pointer.
Queue Created 1 times Number of times this queue was regenerated.
Pakmode Information about internal data structures and parameters.
Pollflags Specifies whether the CDMA queue uses a polling or
interrupt-driven approach for detecting CDMA operation
completion notification.
Note Currently, CDMA queues use interrupt driven completion
only. PDMA queues use interrupt-driven and polling
completion.
Total DMA transactions N umber of DMA transactions in the queue.
Queue create count Number of times this queue was regenerated.
DMA transactions Number of DMA transactions in the queue.
Bytes transferred Number of bytes that have been transferred by the Division
Multiplex Access engine.
DMA Out of Desc errs Number of DMA errors in the queue.
CDMA transactions Number of CDMA transactions in the queue.
DMA IWA Number of IWA bytes that have been processed by the Division
Multiplex Access engine.
DMA transaction errs Number of DMA transactions that had errors.
Descriptor list base addr Internal information about the location of the descriptor list.
Physical address Physical address of the CPU memory that holds the descriptors in
the ring used by the CDMA queue hardware.
list_size Total number of descriptors in the ring used by the CDMA queue
hardware.