Cisco Systems OL-14340-01 manual Matching traffic, AR-89

ASIC Driver Commands on Cisco IOS XR Software

show controllers plim asic spa bay

	Table 16	show controllers plim asic spa bay Field Descriptions (continued)
	Field		Description
	Strict priority mode		Indicates whether strict priority mode is active or inactive on this
			SPA.
			Strict priority mode ensures that the Priority Queue is serviced only
			when it is not empty. This provides the lowest possible delay for
			matching traffic.
	EFC Manager		Indicates whether the EFC2 manager is enabled or disabled on this
			SPA.
	SPA dual wide mode		Indicates whether dual wide mode is active or inactive on this SPA.
	Max SPA channels		Maximum channels supported on this SPA.
	PLIM loopback		Indicates whether loopback is active or inactive on this SPA.
	SPI loopback		Indicates whether SPI loopback is active or inactive on this SPA.
	DatamaxT		Maximum data training interval. This is the maximum interval
			between scheduling of training sequences on the SPI4 data path. If
			the DatamaxT field shows 0, then the core never sends periodic
			training.
	Training M		Number of consecutive DIP-2 errors detected on the Tstat bus
			before the TxSPI module enters the out-of-frame state. This signal
			can be safely set at any time.
	DIP2 Match		Total number of 2-bit DIP23 packets that met specific match
			clauses.
			Note DIP2 is a parity algorithm where a 2-bit odd parity is
			computed diagonally over status words.
	DIP2 Error		Total number of 2-bit DIP2 errors
			Note DIP2 is a parity algorithm where a 2-bit odd parity is
			computed diagonally over status words.
	Tx SClk edge		Indicates which edge of the transmit SClk to use to sample the Tstat
			bus. Selects rising or falling edge as the active transmit SClk edge.
	DIP4 Match		Total number of 2-bit DIP4 packets that met specific match clauses.
	Rx SClk edge		Indicates which edge of the receive SClk to use to sample the Tstat
			bus. Selects rising or falling edge as the active transmit SClk edge.
	DIP4 Error		Total number of DIP4 errors.
			Note DIP4 is a parity algorithm where a 4-bit odd parity is
			computed diagonally over status words.
	SPI bus speed		SPI4 bus speed in MHz5.
	Tx Burst size		Committed burst size in bits for traffic transmitted on this SPA.
	Rx Burst size sysdb		Committed burst size in bits for traffic received on this SPA.
	Rx SPI state		Indicates whether receive SPI is enabled or disabled.
	Rx SPI sync state		Indicates which parameter controls the synchronization behavior of
			the RXSPI module.
	Rx calendar mode		Indicates which RXSPI status protocol will be used to transmit
			status.
			Cisco IOS XR Advanced System Command Reference
OL-14340-01				AR-89