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| show controllers |
| Table 6 | show controllers | |
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|
| Field |
| Description |
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|
| TX PD ring: |
| Indicates the memory location of the beginning of buffer information for the transmit |
|
|
| packet descriptor ring. |
| tx_head_pd |
| Indicates current head packet descriptor. |
| tx_tail_pd |
| Indicates current tail packet descriptor. |
| ehdr |
| Extended MCNS header. |
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|
|
| MIB Statistics: |
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|
|
|
|
| DS fifo full |
| Number of times the downstream input |
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|
| the Cisco uBR900 series. |
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|
|
|
| rerequests |
| Number of times a bandwidth request generated by the Cisco uBR900 series was not |
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|
| responded to by the CMTS. |
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|
| |
| DS mac msg overruns | Number of times the Cisco uBR900 series’ DMA controller had a downstream MAC | |
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|
| message and there were no free MAC message buffer descriptors to accept the message. |
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|
|
| DS data overruns |
| Number of times the Cisco uBR900 series’ DMA controller had downstream data and |
|
|
| there were no free data PDU buffer descriptors to accept the data. |
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|
|
| Qualified maps |
| Number of times a MAP message passed all filtering requirements and was received by |
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|
| the Cisco uBR900 series. |
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|
|
| Qualified syncs |
| Number of times a timestamp message was received by the Cisco uBR900 series. |
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|
| CRC fails |
| Number of times a MAC message failed a cyclic redundancy (CRC) check. |
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|
|
| HDR chk fails |
| Number of times a MAC header failed its |
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| |
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| header even in a collision environment. |
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|
| Data pdus |
| Total number of data PDUs (protocol data units) of all types received by the |
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|
| Cisco uBR900 series. |
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|
| Mac msgs |
| Number of MAC messages received by the Cisco uBR900 series. |
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|
| Valid hdrs |
| Number of valid headers received by the Cisco uBR900 series, including PDU headers, |
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| MAC headers, and headers only. |
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| |
| Global control and status: | Used to reset the BCM3300 chip. | |
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|
| interrupts: |
| Hexadecimal values of the pending IRQ interrupt and IRQ mask. |
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Configuring the Cisco uBR900 Series Cable Access Routers 75
