Triggering
To find the nth assertion of a chip select line
To find the nth assertion of a chip select line
1Select the timing analyzer Trigger menu.
2Define the glitch/edge1 term to represent the asserting transition on the chip select line.
You can rename the Edge1 term to make it correspond more closely to the problem domain, for example, to CHIP_SEL.
3Under Timing Sequence Levels, enter the following sequence specification:
TRIGGER on “CHIP_SEL” 10 times
Triggering on the 10th Assertion of a Chip Select Line
