HP 16500C, 16501A LOGIC Analyzer Problems, Unwanted triggers, Intermittent data errors

Analyzer Problems

This section lists general problems that you might encounter while using the analyzer.

	Intermittent data errors
	This problem is usually caused by poor connections, incorrect signal levels, or
	marginal timing.
	Remove and reseat all cables and probes; ensure that there are no bent
	pins on the preprocessor interface or poor probe connections.
	Adjust the threshold level of the data pod to match the logic levels in the
	system under test.
	Use an oscilloscope to check the signal integrity of the data lines.
	Clock signals for the state analyzer must meet particular pulse shape and
	timing requirements. Data inputs for the analyzer must meet pulse shape and
	setup and hold time requirements.
See Also	See “Capacitive Loading” in this chapter for information on other sources of
	intermittent data errors.

Unwanted triggers

Unwanted triggers can be caused by instructions that were fetched but not executed.

Add the prefetch queue or pipeline depth to the trigger address to avoid this problem.

The depth of the prefetch queue depends on the processor that you are analyzing. Suppose you are analyzing a pipelined processor having fetch, decode, execute, and memory stages. The processor fetches 32-bit words. To ensure that the processor has begun executing a particular routine when the trigger occurs, set the trigger to the module entry address plus 08 hex. (This assumes that there is no immediate data in the instruction stream.)

5–3