Making Measurements

Monitoring Signaling Bits

 

Monitoring Signaling Bits

Description

The HP 37718A receiver can be used to monitor the state of signaling

 

bits in received 2 Mb/s signals with timeslot-16 CAS multiframing

 

(PCM30 or PCM30CRC) and DS1 structured signals.

2.048 Mb/s

For 2 Mb/s signals with timeslot-16 CAS multiframing a table showing

Results

the values of A,B,C,D signaling bits in all 30 channels is given.

DS1 Results

D4 and SLC-96 payloads

 

A table simultaneously showing the state of the A and B signaling bits in

 

the 6th and 12th frames of a superframe is given. Each frame contains

 

24 timeslots. In SLC-96 mode A and B choices are 0, 1 or alternating. If

 

you set bit A or B to alternate, the displayed bit changes to an A, to

 

indicate that the bit is alternating from 1 to 0. The same signaling is

 

transmitted in all channels.

 

ESF Payloads

 

A table simultaneously showing the state of the A, B, C and D signaling

 

bits in the 6th, 12th, 18th and 24th frames of a superframe is given.

 

Each frame contains 24 timeslots.

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HP BER 718 37718A manual Monitoring Signaling Bits, D4 and SLC-96 payloads, ESF Payloads