If you specify this event set and you are on an Integrity servers dual-core Itanium

 

2 or Itanium 9300 quad-core processor system, it is treated as if you specified

 

-m l2dcache,l2icache.

l2dcache

Provides miss rate information for the L2 data cache for Integrity servers

 

dual-core Itanium 2 and Itanium 9300 quad-core processor systems.

l2icache

Provides miss rate information for the L2 instruction cache for Integrity servers

 

dual-core Itanium 2 and Itanium 9300 quad-core processor systems.

l3cache

Provides miss rate information for the L3 unified cache.

overview

Provides a particular set of metrics, depending on whether you are running

 

on an Itanium 2, or a dual-core Itanium 2 or Itanium 9300 quad-core processor

 

server.

Provides these metrics for Itanium 2 Integrity servers:

•stall

•cpi

•dispersal

•l1icache

•l1dcache

•l2cache

•tlb

•fp

This is the same as specifying -m

stall,cpi,dispersal,l1icache,l1dcache,l2cache,tlb,fp

Provides the following metrics for Itanium 2 dual-core and Itanium 9300 quad-core processor Integrity servers:

•stall

•cpi

•dispersal

•l1icache

•l1dcache

•l2icache

•l2dcache

•l3cache

•tlb

•fp

This is the same as specifying -m

stall,cpi,dispersal,l1icache,l1dcache,l2icache,l2dcache,l3cache,tlb,fp

Provides these metrics for Intel® Itanium® 9500 series processor Integrity servers:

•stall

•cpi

•dispersal

•l1icache

•l1dcache

•l2icache

cpu Measurement Report Description 185