page walker (HPW) is invoked to insert the required page into the level 2 TLB, which is then forwarded to the level 1 data TLB.

•L2Dtlb

This counts the number of cycles stalled due to a level 2 data TLB miss during the time the HPW is actively attempting to resolve the requested TLB entry. If the entry is not in the cache, the HPW will terminate and initiate a trap to software to provide the required TLB entry. This component counts the stall component only due to the HPW providing the required TLB entry. Time spent in the software trap handler is not counted in this component.

•Dcache

This counts the number of cycles stalled due to data cache misses at any level of the cache hierarchy (L1, L2, L3). Due to event limitations, it is not possible to distinguish between freg-freg and freg-load dependencies. This has the unfortunate effect of counting either scoreboard cycles as data cache cycles or data access cycles as scoreboard cycles. This implementation allocates all floating-point stalls to the data cache category. This has the implication that some floating-point register dependency stalls that should be allocated to the scoreboard category will be incorrectly allocated to the data cache category.

•RSE Active

This counts the number of cycles that the pipeline is stalled due to the Register Save Engine spilling/filling registers to/from memory.

Metrics Available for Intel® Itanium® 9500 series systems

On Intel® Itanium® 9500 processor systems, the metrics "Branch" (under FE components), BE Flush, Scoreboard, L1Dtlb , L2Dtlb and Dcache are replaced by the metrics described below.

•FE Misc

Percentage of backend cycles stalled that were due to the frontend, caused by reasons other than instruction access.

•Reg Loads

Percentage of backend cycles stalled because of register loads.

•BE Replay

Percentage of backend cycles stalled due to various replays.

•BE Sched

Percentage of backend cycles lost to scheduling stalls (floating point and load-to-load address scheduling stalls).

•Branch

Percentage of backend cycles stalled due to writeback (WB2) flushes, indirectly attributable to branches.

•BE Misc

Percentage of backend cycles lost due to other stalls in the backend.

sysbus Event Set

Available only on Itanium 2 and dual-core Itanium 2 systems.

The sysbus event set provides data on system bus utilization and its breakdown into:

•Transaction originator (all, local cpu, io)

•Transaction type (brl, bril, bil, bwl, partial)

If you use this option, you must use the --bus-speedoption.

If you use this event set, the default is to make the measurements irrespective of CPU operating state (that is, user, system, or interrupt states). By default, the idle state is not included in the

sysbus Event Set 261