measurement. You can use
•Limit measurement to a specific privilege level:
•Include idle:
•Exclude the interruption state:
•Only measure the interruption state:
Metrics Available from this Measurement
The following metrics are available from this event set. These descriptions do not take into account any
The metrics are:
•Avg Lat
Average memory read latency provides a measure of the number of CPU cycles required to service a memory cache line read from the perspective of the bus request queue (BRQ). The time measured includes the arbitration cycles, address cycles, memory controller/memory cycles, and data return cycles.
The reported average latency will be incorrect on Itanium 2 steppings earlier than B2.
The average memory read latency on the
•Avg Outstand
Average number of outstanding reads per cycle gives some idea of the memory request density, that is, the probability of one or more memory requests per cycle. For
The reported average latency value will be incorrect on Itanium 2 steppings earlier than B2.
•CPU
CPU transaction component is a measure of the percentage of all bus transactions generated by all CPUs on a shared front side bus (FSB).
•I/O
I/O transaction component is a measure of the percentage of all bus transactions initiated by any I/O agent on a shared FSB.
•Util Adrs
Average address bus utilization gives an estimate of total address bus utilization resulting from all bus transactions to include cache misses, I/O port reads/writes, interprocessor interrupts, writebacks, cache line invalidates (FC instruction, store hit on shared line), and clean castouts (if enabled). The utilization is computed as follows:
ADRS UTIL = 100.0 * (total transactions/sec * 3.0) / bus cycles/sec
The constant value (3.0) is the number of address cycles needed for each bus transaction.
262 Event Set Descriptions for CPU Metrics