•BE_FLUSH_BUBBLE.ALL — The number of Full Pipe Bubbles in Main Pipe due to pipeline flushes. This is the number of cycles lost (stall cycles) due to branch misprediction or exception/interruption flush.

•BE_L1D_FPU_BUBBLE.L1D — The number of Full Pipe Bubbles in Main Pipe due to L1D cache. This is the number of cycles lost (stall cycles) due to L1D cache and L1/L2 DTLB.

•CPU_OP_CYCLES.ALL — The number of elapsed CPU operating cycles.

When HyperThreading is on, this is the number of elapsed CPU operating cycles used by only this process's hyperthread.

•CPU_OP_CYCLES.ALL:all_threads=true

The number of elapsed CPU operating cycles used by both hyperthreads. Available only when HyperThreading is on.

•IA64_INST_RETIRED — The number of retired IA-64 instructions. The count includes predicated on and predicated off instructions and nops, but excludes hardware-inserted RSE operations.

•NOPS_RETIRED — The number of retired nop.i, nop.m, or nop.b instructions. The count excludes predicated off nop instructions.

•PREDICATE_SQUASHED_RETIRED — The number of predicated off instructions retired.

•THREAD_SWITCH_EVENTS.ALL — The number of hardware thread switches.

•THREAD_SWITCH_EVENTS.L3MISS — The number of hardware thread switches due to L3 cache miss.

The following CPU metrics are derived (calculated) from the above CPU events:

•% of Cycles lost due to stalls (lower is better) — The percentage of cycles lost due to all stalls.

•% of Cycles lost due to stalls caused by L1D (L1D and L1/L2 DTLB) — The percentage of cycles lost due to L1D cache and L1/L2 DTLD.

•% of Cycles lost due to GR/GR or GR/load dependency stalls — The percentage of cycles lost due to GR/load or GR/GR dependency stalls.

•% of Cycles lost due to branch misprediction or interruption flush stalls — The percentage of cycles lost due to branch misprediction or interruption flush.

•Effective instructions retired — The number of effective instructions retired excluding nop and predicated off instructions.

•Raw CPI (lower is better) — The cycles per instruction, including nop and predicated off instructions.

•Effective CPI (lower is better) — The cycles per effective instruction, excluding nop and predicated off instructions.

•Effective CPI during unstalled execution (lower is better) — The cycles per effective instruction, excluding stall cycles, nop, and predicated off instructions.

•% of thread switches due to L3 misses — The hardware thread switches can happen due to various reasons including L3 cache misses and timer events. This metric provides the percentage of thread switches due to L3 cache misses.

•% Core cycles due to this thread — This indicates the percentage of available processor cycles that the measured process consumed. The other processor cycles were consumed by other process(es) running in the core's other hyperthread or were lost to HyperThreading overhead.

Metrics for Integrity Servers Intel® Itanium® 9500 Processors Systems

•RETIRED_INST_NOP — The number of No-ops retired.

•IA64_INST_RETIRED — The number of retired IA-64 instructions.

•RETIRED_PREDICATE_SQUASHED — The number of retired instructions with predicate off.

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