◦unstall
HPW insert or MLD return or IBQ not empty.
◦timeslice
completion of the allocated timeslice of the executing thread.
•Stall
Cycles spent in stalls during threadswitches.
tlb Event Set
The tlb event set provides information related to translation lookaside buffer (TLB) misses.
The Itanium 2 TLB implementation is split for instructions and data, with two levels for each. The first level only maps 4K pages. Thus, the miss rate (per sec/per kinst) might be quite high. The second level supports large pages and is backed up by hardware that automatically inserts the required translation if it is found to be the head element on the page table list. The hardware insertion hardware does not traverse the page table list. If the required translation is not the first translation on the page list, it will trap to software to perform the update.
If you use this event set, the default is to make the measurements irrespective of CPU operating state (that is, user, system, or interrupt states). By default, the idle state is not included in the measurement. You can use
•Limit measurement to a specific privilege level:
•Include idle:
•Exclude the interruption state:
•Only measure the interruption state:
The event per kinst (event per 1000 instructions) metrics are computed using all instructions retired. This includes nops, predicated off instructions, failed speculation and instructions and associated recovery code as well as the architecturally visible instruction. You can eliminate idle loops effects by using the
Metrics Available from this Measurement
The following metrics are available from this event set. These descriptions do not take into account any
The metrics are:
•I1TLB Misses Per Sec
This is the number of level 1 ITLB misses per second. This level of the ITLB only operates with 4K pages. Thus, its miss rate will be high, but it is normally the case that any required translation would be provided by the level 2 ITLB in three cycles.
•I2TLB Misses Per Sec
This is the number of level 2 ITLB misses per second. A miss at this level will attempt to be serviced by the hardware page walker (HPW). If the required translation is at the head of the hash table, the hardware automatically inserts the translation into the I2TLB. If the required translation is not the head element, a trap will be taken to the software TLB handler to perform the requisite update.
266 Event Set Descriptions for CPU Metrics