HP UX IPFilter Software Cycles lost due to pipeline-flush stalls, Cycles lost due to RSE stalls

BE_EXE_BUBBLE.GRGR

BE_FLUSH_BUBBLE.ALL

BE_L1D_FPU_BUBBLE.ALL

BE_L1D_FPU_BUBBLE.L1D

BE_RSE_BUBBLE.ALL

CPU_OP_CYCLES.ALL

CPU_OP_CYCLES.ALL:all_threads=true

%Unstalled execution (higher is better)

%of Cycles lost due to frontend stalls (lower is better)

%of Cycles lost due to Pipeline flush stalls (lower is better)

%of Cycles lost due to data access stalls (lower is better)

%of Cycles lost due to RSE stalls (lower is better)

%of Cycles lost due to Scoreboard stalls (lower is better)

%of Cycles lost due to front-end stalls

%of Cycles lost due to pipeline-flush stalls

%of Cycles lost due to data access stalls (includes FR/FR stalls)

%of Cycles lost due to RSE stalls

%of Cycles lost due to Scoreboard stalls (excludes FR/FR stalls)

%of Cycles lost due to register load stalls (includes FR/FR stalls)

%of Cycles lost due to FR/load or FR/FR dependency stalls

%of Cycles lost due to GR/load dependency stalls

%of Cycles lost due to stalls in L1D cache and L1/L2 DTLB

cycles) due to general register/general register or general register/load dependency.

Full Pipe Bubbles in Main Pipe due to GR/GR dependency stalls. This is the number of cycles lost (stall cycles) due to GR/GR dependency stalls.

Full Pipe Bubbles in Main Pipe due to pipeline flushes. This is the number of cycles lost (stall cycles) due to branch misprediction or exception/interruption flush.

Full Pipe Bubbles in Main Pipe due to L1D cache. This is the number of cycles lost (stall cycles) due to L1D cache and L1/L2 DTLB.

Full Pipe Bubbles in Main Pipe due to RSE stalls. Percentage of cycles lost due to stalls in RSE spilling/filling registers to/from memory.

Number of elapsed CPU operating cycles. (Note: This event is called CPU_CYCLES on Itanium 2 systems.)

When HyperThreading is on, this is the number of elapsed CPU operating cycles used by only this process's hyperthread.

Number of elapsed CPU operating cycles used by both hyperthreads. Available only when HyperThreading is on.

Percentage of unstalled cycles with respect to total number of elapsed CPU operating cycles.

Percentage of cycles lost due to instruction cache, ITLB, and branch execution stalls.

Percentage of cycles lost due to branch misprediction or interruption flush.

Percentage of stall cycles lost due to DCACHE and DTLB stalls.

Percentage of cycles lost due to stalls in RSE spilling/filling registers to/from memory.

Percentage of stall cycles lost due to FPU and register dependency stalls. It excludes FR/FR dependency stalls.

Percentage of stall cycles lost due to front-end stalls. Percentage of stall cycles lost due to pipeline-flush stalls.

Percentage of cycles lost due to data access stalls. It includes FR/FR dependency stalls.

Percentage of stall cycles lost due to RSE stalls.

Percentage of stall cycles lost due to FPU and register dependency stalls. It excludes FR/FR dependency stalls.

Percentage of cycles lost due to register load stalls. It includes FR/FR dependency stalls.

Percentage of cycles lost due to FR/FR or FR/load dependency stalls.

Percentage of cycles lost due to GR/load dependency stalls.

Percentage of cycles lost due to L1D cache and L1/L2 DTLB.

traps Measurement Report Description 229