%of Cycles lost due to frontend stalls (lower is better)
%of Cycles lost due to Pipeline flush stalls (lower is better)
%of Cycles lost due to data access stalls (lower is better)
%of Cycles lost due to RSE stalls (lower is better)
%of Cycles lost due to Scoreboard stalls (lower is better)
%of Cycles lost due to register load stalls (includes FR/FR stalls)
%of Cycles lost due to FR/load or FR/FR dependency stalls
%of Cycles lost due to GR/load dependency stalls
%of Cycles lost due to stalls in L1D cache and L1/L2 DTLB
%of Cycles lost due to register dependency stalls (excludes FR/FR stalls)
%of Cycles lost due to GR/GR dependency stalls
%of Cycles lost due to FPU
% Core cycles due to this thread
Percentage of cycles lost due to
Percentage of cycles lost due to branch misprediction or interruption flush.
Percentage of stall cycles lost due to DCACHE and DTLB stalls.
Percentage of cycles lost due to stalls in RSE spilling/filling registers to/from memory.
Percentage of stall cycles due to FPU and register dependency stalls. It excludes FR/FR dependency stalls.
Percentage of cycles lost due to register load stalls. It includes FR/FR dependency stalls.
Percentage of cycles lost due to FR/FR or FR/load dependency stalls.
Percentage of cycles lost due to GR/load dependency stalls.
Percentage of cycles lost due to L1D cache and L1/L2 DTLB.
Percentage of cycles lost due to register dependency stalls. It exclude FR/FR dependency stalls.
Percentage of cycles lost due to GR/load dependency stalls.
Percentage of cycles lost due to
This indicates the percentage of available processor cycles that the measured process consumed. The other processor cycles were consumed by other process(es) running in the core's other hyperthread or were lost to HyperThreading overhead.
Metrics for Integrity Servers Intel® Itanium® 9500 Processors Systems
IA64_INST_RETIRED | The number of retired |
RETIRED_INST_NOP | The number of |
RETIRED_PREDICATE_SQUASHED | The number of retired instructions with predicate off. |
CPU_OP_CYCLES.ALL | The number of elapsed CPU operating cycles. |
CYC_BE_BUBBLE.ANY | The number of CPU cycles lost to replays, flushes or bubbles, |
| including partial replay cycles. |
CYC_BE_WB2_FLUSH.ANY | The number of CPU cycles spent in WB2 (Write back) |
| flushing of instructions. |
CYC_BE_IBD_STALL.ANY | The number of CPU cycles spent in the IBD(instruction buffer |
| and dispersal) without issuing instructions. |
CYC_BE_IBD_STALL.GR_LOAD | This is the number of cycles lost (stall cycles) due to GR load |
| RAW or WAW dependency condition of the instruction. |
CYC_BE_EXE_REPLAY.GR_LOAD_RAW | This is the number of cycles lost (stall cycles) in replay due |
| to RAW hazard in an instruction's GR load. |
CYC_BE_EXE_REPLAY.GR_LOAD_WAW | This is the number of cycles lost (stall cycles) in replay due |
| to WAW hazard in an instruction's GR load. |
CYC_BE_DET_REPLAY.GR_LOAD | This is the number of cycles lost (stall cycles) in replay due |
| to memory loads of single cycle GR load instructions. The |
| loads do not hit the FLD (first level data cache) and have to |
212 Descriptions of Measurement Reports