CYC_BE_IBD_STALL.GR_LOAD | Number of Backend IBD bubbles due to GR load RAW or |
| WAW condition; starts after an EXE replay or DET replay. |
DTLB_HPWREQ_BLK_MISS.FAIL | Number of Blocking walk missed the DTB, HPW walk failed. |
CYC_BE_EXE_REPLAY.GR_LOAD_RAW | Number of Backend EXE replay cycles due to GR load RAW; |
| a new instruction has a source register targeted by an |
| outstanding load, or outstanding long latency move, or TLB |
| related operation. |
IA64_INST_RETIRED | Number of instructions retired. |
CYC_BE_EXE_REPLAY.GR_LOAD_WAW | Backend EXE replay cycles due to GR load WAW; a new |
| instruction has a destination register targeted by an |
| outstanding load, or outstanding long latency move, or TLB |
| related operation. |
CPU_OP_CYCLES.ALL | CPU |
CYC_BE_DET_REPLAY.GR_LOAD | Backend DET replay cycles roughly due to single cycle GR |
| load hazards for loads that do not hit in FLD. (More |
| precisely, DET replay cycles for |
| producer" to use bypasses that do not either hit FLD or DCS. |
| Memory op producer: |
| (M1+M2+M3).ldc_op# + M16 + M17 + M19 + |
| M31.mov_from_urnat# + M33 + M34 + M36 + M38 + |
| M39 + M43 + M46 + M1002). Includes replay cycles due |
| to specualtive predicate replays. |
CYC_BE_BUBBLE.ANY | Number of Backend cycles stalled. |
% Cycles lost due to all stalls (lower | Percentage of cycles lost due to all stalls. |
is better) |
|
%Cycles lost due to GR load penalties
Percentage of cycles lost due to GR load stalls.
Total L1 data TLB references | Number of L1 data TLB references. |
% miss of L1 data TLB loads | Percentage of L1 data TLB loads missed |
L2 data TLB misses | Number of L2 data TLB misses. |
% L2 data TLB miss | Percentage of L2 data TLB missed |
% Data references covered by L1 and | Percentage of data references that was satisfied in L1 DTLB |
L2 DTLB | or L2 DTLB. |
% Data references covered by the | Percentage of data references that were satisfied by the |
HPW | hardware page walker (HPW). |
% Data references covered by | Percentage of data references that were serviced by the |
software trap | software trap handler for the TLB misses fault. |
% L2 DTLB misses covered by the | Percentage of L2 DTLB misses covered by the HPW. |
HPW |
|
L1 DTLB miss per 1000 instructions | Number of L1 DTLB miss per 1000 instructions retired. |
retired |
|
L2 DTLB miss per 1000 instructions | Number of L2 DTLB miss per 1000 instructions retired. |
retired |
|
dtlb Measurement Report Metrics
See Table 22 (page 205).
In this table, “program object” refers to any of the following:
•Thread
•Load module
•Function
204 Descriptions of Measurement Reports