•64–255

Percentage of thread switches that were triggered after the processor had stalled for 64 to 255 cycles. A non-zero value represents wasted processor cycles.

•>=256

Percentage of thread switches that were triggered after the processor had stalled for 256 or more cycles. A non-zero value represents wasted processor cycles.

•Overhead Cycles Per Sec

Number of processor cycles per second consumed by the thread switching itself. A large value indicates that many cycles were lost to the process in overhead.

•Gated Cycles Per Sec

Number of processor cycles per second that a pending thread switch was held up waiting for some blocking condition to clear.

Metrics Available for Intel® Itanium® 9500 series systems

The metrics are:

•TS Per Sec in FE

Number of threadswitches in the frontend of the pipeline.

•TS Per Sec in BE

Number of threadswitches in the backend of the pipeline.

•TS Per Kinst in FE

Number of threadswitches every 1000 instructions in the frontend of the pipeline.

•TS Per Kinst in BE

Number of threadswitches every 1000 instructions in the backend of the pipeline.

•Cause of threadswitch in the FE:

◦

◦

Hint hint@BSWT

Stall

an MLD miss or Data TLB miss or Instruction Buffer Empty.

◦unstall

MLI returning from certain events like write back.

◦timeslice

completion of the allocated timeslice of the executing thread.

•Cause of threadswitch in the BE:

◦

◦

Hint hint@Pause

Stall

MLD use or HPW miss or IBQ being empty.

threadswitch Event Set 265