L1ITLB_INSERTS_HPW

L1I_READS

%of Cycles lost due to all stalls (lower is better)

%of Cycles lost due to frontend stalls (ICACHE, ITLB, and branch execution)

%of Cycles lost due to instruction TLB stalls

%of Cycles lost due to instruction cache stalls

%of Cycles lost due to instruction access stalls (ICACHE and ITLB)

%of Cycles lost due to branch execution

Total L1 instruction TLB references

L1 instruction TLB miss percentage

L2 instruction TLB misses

Percentage of L2 ITLB misses covered by the HPW

L1 ITLB miss per 1000 instructions retired

L2 ITLB miss per 1000 instructions retired

Number of instruction TLB inserts done by the hardware page walker (HPW).

The number of data memory read references issued into the memory pipeline that are serviced by L1D (only integer loads), RSE loads, L1-hinted loads (L1D returns data if it hits in L1D but does not do a fill), and check loads (ld.c). Non-cacheable reads, VHPT loads, semaphores, floating-point loads, and lfetch instructions are not counted here because L1D does not handle these. The count includes wrong path operations but excludes predicated off operations.

Percentage of cycles lost due to all stalls.

Pecentage of cycles lost due to ICACHE, ITLB and branch execution stalls.

Percentage of cycles lost due to instruction TLB miss stalls.

Perdcentage of cycles lost due to instruction cache miss stalls.

Perdcentage of cycles lost due to instruction cache miss and instruction TLB miss stalls.

Percentage of cycles lost due to branch execution (branch re-steer).

Number of L1 instruction TLB references.

Percentage of L1 instuction TLB accesses that missed. Number of L2 instruction TLB misses.

Percentage of L2 ITLB misses that were serviced by the hardware page walker (HPW).

Number of L1 ITLB misses per 1000 instructions retired.

Number of L2 ITLB misses per 1000 instructions retired.

Metrics for Integrity Servers Dual-Core Intel® Itanium® 9500 Processors Systems

FLITLB_MISS

Demand fetch missed in the L1 or first level instruction TLB

 

(FLITLB) and caused an IPC lookup.

MLITLB_MISS

L2 or mid-level instruction TLB (MLITLB) miss.

FLI_READ.DMND

FLI demand fetch reads.

IA64_INST_RETIRED

Number of retired IA-64 instructions. The count includes

 

predicated on and predicated off instructions and nops,

 

and excludes hardware-inserted RSE operations.

MLITLB_HPW_ABORTS

MLI TLB hardware page-walker aborts.

CYC_BE_BUBBLE.ANY

Number of cycles lost to replays, flushes or stalls, including

 

partial replay cycles.

CPU_OP_CYCLES.ALL

Number of elapsed CPU operating cycles.

CYC_BE_IBD_STALL.ANY

Number of cycles lost to backend IBD bubbles for any

 

reason.

CYC_BE_IBD_STALL.FEBUB

Number of backend bubbles due to FE bubbles - the

 

instruction fetch engine has not provided anything to issue.

itlb Measurement Report Description 221