•%Miss - All
This is the percentage of the total misses (instruction demand fetch misses and instruction prefetch misses) out of the total number of L1 instruction accesses (instruction demand fetch and instruction prefetch). The prefetches include both streaming and
•%Miss - Dfetch
This is the percentage of the number of demand instruction fetch misses out of the total instruction demand fetch accesses.
•%Miss - Pfetch
This is the percentage of the number of instruction prefetch misses out of the total number of instruction prefetch requests. The instruction prefetch count includes streaming and
l2cache Event Set
The l2cache event set provides miss rate information for the L2 unified cache on Itanium 2 systems.
This measurement is valid only on Itanium 2 systems. On
The L2 cache metrics include miss information for instruction prefetch requests, instruction demand requests, integer loads that miss the L1 cache, memory operations not handled by the L1 cache (that is, integer stores), lfetch instructions, and
There are a number of issues regarding L2 cache access that need to be considered when interpreting L2 cache measurement results. The L2 cache will not count fetches to the second half of a line if the fetch for the first part is already counted. Secondary misses are counted as data references, and semaphore operations are counted as a single atomic operation. Only requests that have entered the OZ queue are counted. And these instructions are not counted: FROM_CCV, SETF, PTC_G, FWB, MF, MFA, SYNCI, SYNCIA, PTCM, FC, and CC.
If you use this event set, the default is to make the measurements irrespective of CPU operating state (that is, user, system, or interrupt states). By default, the idle state is not included in the measurement. You can use
•Limit measurement to a specific privilege level:
•Include idle:
•Exclude the interruption state:
•Only measure the interruption state:
The event per kinst (event per 1000 instructions) metrics are computed using all instructions retired. This includes nops, predicated off instructions, failed speculation and instructions and associated recovery code as well as the architecturally visible instruction. You can eliminate idle loops effects by using the
Metrics Available from this Measurement
The following metrics are available from this event set. These descriptions do not take into account any
248 Event Set Descriptions for CPU Metrics