L1 instruction cache misses per 1000

Number of instructions retired per L1 instruction cache miss.

instructions retired

 

L1 instruction prefetch misses per

Number of instructions retired per L1 instruction prefetch

1000 instructions retired

miss.

L1 instruction demand misses per

Number of instructions retired per L1 instruction demand

1000 instructions retired

fetch miss.

L2 instruction cache misses per 1000

Number of instructions retired per L2 instruction cache miss.

instructions retired

 

L2 instruction prefetch misses per

Number of instructions retired per L2 instruction prefetch

1000 instructions retired

miss.

L2 instruction demand misses per

Number of instructions retired per L2 instruction demand

1000 instructions retired

fetch miss.

Metrics for Integrity Servers Intel® Itanium® 9500 Processors Systems

CPU_OP_CYCLES.ALL

CYC_BE_IBD_STALL.ANY

FLI_READ.PREF

FLI_READ.DMND

MLI_READ.ANY_ANY

MLI_READ.ANY_PREF

MLI_READ.ANY_DMND

MLI_READ.MISS_DMND

CYC_BE_BUBBLE.ANY

IA64_INST_RETIRED

CYC_BE_IBD_STALL.FEBUB

MLI_READ.MISS_ANY

MLI_READ.MISS_PREF

CYC_BE_NO_BUBBLE

%of Cycles lost due to all stalls (lower is better)

Cycles lost due to issue bubbles (lower is better)

Cycles lost due to frontend bubbles (lower is better)

L1 instruction cache references

L1 instruction cache misses

%L1 instruction cache miss

%L1 instruction cache prefetch misses

%L1 instruction cache demand misses

L2 instruction cache demand misses

L2 instruction cache prefetch misses

Number of elapsed CPU operating cycles.

Number of cycles lost to backend IBD bubbles for any reason.

L1 or first level instruction cache (FLI) prefetch requests. FLI demand fetch reads.

L2 or mid-level instruction cache (MLI) read all: demand or prefetch.

MLI read all prefetch. MLI read all demand. MLI read miss demand.

Number of cycles lost to replays, flushes or stalls, including partial replay cycles.

Number of retired IA-64 instructions. The count includes predicated on and predicated off instructions and nops, but excludes hardware-inserted RSE operations.

Number of backend bubbles due to FE bubbles - the instruction fetch engine has not provided anything to issue.

MLI read miss: demand or prefetch. MLI read miss prefetch.

Number of cycles an entire issue group was able to retire. Percentage of cycles lost due to all stalls.

Number of cycles lost due to issue bubbles.

Number of cycles lost due to frontend bubbles.

Number of references to FLI cache.

Number of FLI cache misses.

Percentage of FLI cache misses.

Percentage of FLI cache prefetch misses.

Percentage of FLI cache demand misses.

Number of MLI cache demand misses.

Number of MLI cache prefetch misses.

icache Measurement Report Description 217