Metrics Available for Intel® Itanium® 9500 series systems
•Total misses per second
This is the total number of L3 cache misses per second. It includes all instruction misses and data misses.
•Inst - Misses Per Second
This is the number of instruction requests that miss the L3 cache per second.
•Data - Misses Per Second
This is the number of data requests that miss the L3 cache per second.
•Total misses per kinst
This is the total number of L3 cache misses per 1000 retired instructions, including nops. It includes all instruction misses and data misses.
•Inst - Misses Per kinst
This is the number of instruction requests that miss the L3 cache per 1000 retired instructions.
•Data - Misses Per kinst
This is the number of data requests that miss the L3 cache per 1000 retired instructions.
•Instr Per Access
This is the ratio of the total number of instructions retired per L3 unified cache access. The instruction count includes nops and predicated off instructions. Accesses include all memory reference operations to include load/stores, RSE loads/stores, and instruction fetch/prefetches that miss higher levels of the cache hierarchy.
•%Miss
This is the percentage of the total number of L3 unified accesses that miss the L3 cache out of the total number of L3 accesses. The L3 is accessed by all loads/stores, RSE loads/stores, and instruction fetches/prefetches that miss higher levels of the cache hierarchy.
memreq Event Set
Available only on Itanium 9300
The memreq event set provides data about memory read latency and cacheable and uncacheable memory requests.
If you use this event set, the default is to make the measurements irrespective of CPU operating state (that is, user, system, or interrupt states). By default, the idle state is not included in the measurement. You can use
•Limit measurement to a specific privilege level:
•Include idle:
•Exclude the interruption state:
•Only measure the interruption state:
Metrics Available from this Measurement
The following metrics are available from this event set. These descriptions do not take into account any
memreq Event Set 255