IBM 440 manual Cec

CEC 1 CEC 2

CPU 1 CPU 2 CPU 3 CPU 4

400 MHz		3.2 GBps
32 MB		Processor &
L4 cache	3.2 GBps	cache controller

SMP Expansion Ports (3.2GBps)

CPU 4		CPU 3	CPU 2		CPU 1
	3.2 GBps			400 MHz
Processor &					32 MB
cache controller			3.2 GBps		L4 cache

		3.2 GBps
SDRAM	3.2 GBps
		Memory
SDRAM		controller
	3.2
	GBps
SDRAM		2 GBps
SDRAM	100 MHz

RXE

Expansion

Port B

(1 GBps)

3.2 GBps

Memory controller

2 GBps

3.2GBps

3.2 GBps

100 MHz

SDRAM SDRAM

SDRAM SDRAM

RXE Expansion	PCI bridge	66 MHz
Port A (1 GBps)

Bus A

PCI bridge

66 MHz

Ultra160

SCSI

Gigabit

Ethernet

33MHz

Video

USB

Kbd/Ms

RSA

B-100 C-133 D-133

IBM XA-32 core chipset

64-bit	64-bit	64-bit
66 MHz	100 MHz	133 MHz

Figure 1-5 xSeries 440 system block diagram — two SMP Expansion Modules

When two SMP Expansion Modules are installed, they are connected together using two 3.2 GBps SMP Expansion Ports. The third scalability port is not used in this single-node eight-way configuration.

The two PCI bridges in the XA-32 chipset provide support for 33, 66, 100, and

133MHz devices using four PCI-X buses (labeled A-D in Figure 1-5). This is discussed further in 1.8, “PCI subsystem” on page 23.

The PCI bridge also has a 1 GBps bi-directional Remote Expansion I/O port (RXE port) for connectivity to the RXE-100 enclosure. This port is labeled “RXE Expansion Port A” in both Figure 1-4 on page 8 (four-way) and Figure 1-5 (eight-way). The RXE-100 provides up to an additional 12 PCI-X slots. When the second SMP Expansion Module is installed to form an eight-way system (Figure 1-5), the second RXE port, labeled “RXE Expansion Port B”, connects to the memory controller of the second SMP Expansion Module.

10 IBM ^xSeries 440 Planning and Installation Guide