Manuals / Intel / Computer Equipment / Computer Hardware

Intel 8XC196NT, 87C196CB Selecting Bank 0 FF2000-FF7FFFH, Selecting Bank 1 FF8000-FFFFFFH

Models: 8XC196NT 87C196CB

1 155

Download 155 pages 42.65 Kb

Page 119

87C196CB SUPPLEMENT

Table 10-4. Serial Port Programming Mode Memory Map

	Description		Address Range

		Normal Operation	Serial Port Programming Mode
		Normal Operation	Serial Port Programming Mode

	Internal OTPROM	FF2000–FF7FFFH	A000–FFFFH (bank 0; 1FF9H = 00H)
	Internal OTPROM	FF8000–FFFFFFH	8000–FFFFH (bank 1; 1FF9H = 80H)
		FF8000–FFFFFFH	8000–FFFFH (bank 1; 1FF9H = 80H)

	External memory	—	4000–7FFFH

	Do not address	—	2400–3FFFH

	Test ROM and RISM	—	2000–23FFH

The lower 24 Kbytes of OTPROM (FF2000–FF7FFFH) are remapped to A000–FFFFH, and the upper 32 Kbytes (FF8000–FFFFFFH) are mapped to 8000–FFFFH. A bank switching mecha- nism differentiates between the two address ranges. The most-significant bit of an otherwise re- served byte register (location 1FF9H) selects the bank. Bank 0 is the lower 24 Kbytes, and bank 1 is the upper 32 Kbytes. To program the lower 24 Kbytes, you must write 00H to location 1FF9H. To program the upper 32 Kbytes, you must write 80H to location 1FF9H. (See page 10-4 for the required command sequences.)

WARNING

Writing any value other than 00H or 80H to location 1FF9H will cause the microcontroller to enter an unsupported test mode.

10.4.1 Selecting Bank 0 (FF2000–FF7FFFH)

Send the following RISM command sequence to select bank 0.

Code Description

1F DATA. High byte of address to DATA register.

F9 DATA. Low byte of address to DATA register.

0A DATA_TO_ADDR. Move address from DATA register to ADDR register.

00SET_DLE_FLAG. The next data byte is <1FH.

00DATA. Data to clear the most-significant bit.

07WRITE_BYTE. Move data from the DATA register to memory location 1FF9H.

10.4.2 Selecting Bank 1 (FF8000–FFFFFFH)

Send the following RISM command sequence to select bank 1.

Code Description

1F DATA. High byte of address to DATA register.

F9 DATA. Low byte of address to DATA register.

0A DATA_TO_ADDR. Move address from DATA register to ADDR register.

80 DATA. Data to set the most-significant bit.

07 WRITE_BYTE. Move data from the DATA register to memory location 1FF9H.

10-4

Image 119

Intel 8XC196NT, 87C196CB Selecting Bank 0 FF2000-FF7FFFH, Selecting Bank 1 FF8000-FFFFFFH, Serial Port Programming Mode

Contents

87C196CB Supplement to 8XC196NT User’s Manual Order Number 87C196CB Supplement to 8XC196NT User’s ManualAugust Copyright Intel Corporation, 1998 CHAPTER CONTENTSCHAPTER GUIDE TO THIS MANUALSPECIAL OPERATING MODES SIGNAL DESCRIPTIONS87C196CB SUPPLEMENT CHAPTEREffect of Clock Mode on CLKOUT Frequency FIGURESCONTENTS Internal Clock Phases87C196CB 100-pin QFP Package FIGURES8XC196CB SUPPLEMENT PagePage TABLESCONTENTS Page Guide to This Manual Page CHAPTER GUIDE TO THIS MANUAL 1.1 MANUAL CONTENTSChapter 9 - Interfacing with External Memory 1.2 RELATED DOCUMENTSAppendix A - Signal Descriptions Architectural Overview Page CHAPTER ARCHITECTURAL OVERVIEW 2.1 DEVICE FEATURES2.3 INTERNAL TIMING 2.2 BLOCK DIAGRAMPage 20 MHz 8 MHz12 MHz 16 MHzInput Frequency to Figure 2-4. Effect of Clock Mode on CLKOUT FrequencyARCHITECTURAL OVERVIEW FrequencyPage Memory Partitions Page 3.1 MEMORY MAP, SPECIAL-FUNCTION REGISTERS, AND WINDOWING CHAPTER MEMORY PARTITIONSAddress 87C196CB SUPPLEMENT Table 3-2. 87C196CB Memory MapSIO and SSIO SFRs Timer 1, Timer 2, and EPA SFRsMEMORY PARTITIONS Table 3-3. 87C196CB Peripheral SFRs Ports 0, 1, 2, and 6 SFRs1ECCH 87C196CB SUPPLEMENT Table 3-4. CAN Peripheral SFRs1EDCH Message MEMORY PARTITIONS Table 3-4. CAN Peripheral SFRs Continued128-byte Window 87C196CB SUPPLEMENT Table 3-5. Selecting a Window of Peripheral SFRs32-byte Window 64-byte WindowLocations MEMORY PARTITIONSTable 3-6. Selecting a Window of the Upper Register File Register RAM87C196CB SUPPLEMENT 0DE0-0DFFH MEMORY PARTITIONSTable 3-7. Selecting a Window of Upper Register RAM 87C196CB SUPPLEMENT Table 3-8. Windows Upper Register File MEMORY PARTITIONSTable 3-8. Windows Continued 87C196CB SUPPLEMENT Table 3-9. WSR Settings and Direct Addresses for Windowable SFRsMEMORY PARTITIONS 87C196CB SUPPLEMENT MEMORY PARTITIONS 87C196CB SUPPLEMENT MEMORY PARTITIONS 87C196CB SUPPLEMENT 128-byte Windows MEMORY PARTITIONS32-byte Windows 64-byte Windows32-byte Windows Standard and PTS Interrupts Page 4.1 INTERRUPT SOURCES, VECTORS, AND PRIORITIES CHAPTER STANDARD AND PTS INTERRUPTSStandard Vector 87C196CB SUPPLEMENTFigure 4-1. Interrupt Mask 1 INTMASK1 Register Figure 4-2. interrupt Pending 1 INTPEND1 RegisterI/O Ports Page 5.1 PORT 0 AND EPORT CHAPTER I/O PORTSEPDIR Figure 5-3. Extended Port Mode EPMODE Register87C196CB SUPPLEMENT Figure 5-2. Extended Port I/O Direction EPDIR RegisterEPPIN I/O PORTSFigure 5-4. Extended Port Input EPPIN Register Figure 5-5. Extended Port Data Output EPREG RegisterPage Analog-to-digital A/D Converter Page 6.1 ADDITIONAL A/D INPUT CHANNELS CHAPTER 6 ANALOG-TO-DIGITAL A/D CONVERTERFunction Figure 6-1. A/D Command ADCOMMAND RegisterADCOMMAND 87C196CB SUPPLEMENTFunction ANALOG-TO-DIGITAL A/D CONVERTERFigure 6-2. A/D Result ADRESULT Register - Read Format ADRESULT ReadPage CAN Serial Communications Controller Page 7.1 CAN FUNCTIONAL OVERVIEW CHAPTER 7 CAN SERIAL COMMUNICATIONS CONTROLLERPage Table 7-2. Control and Status Registers 7.2 CAN CONTROLLER SIGNALS AND REGISTERSTable 7-1. CAN Controller Signals CAN SERIAL COMMUNICATIONS CONTROLLER87C196CB SUPPLEMENT Table 7-2. Control and Status Registers Continued 7.3 CAN CONTROLLER OPERATION7.3.2 Message Objects 7.3.1 Address Map7.3.2.2 Message Acceptance Filtering Contents87C196CB SUPPLEMENT Table 7-4. Message Object Structure 7.3.2.1 Receive and Transmit Priorities7.3.3 Message Frames Table 7-7. Extended Message Frame 87C196CB SUPPLEMENT Table 7-6. Standard Message Frame7.3.4 Error Detection and Management Logic Definition 7.3.5 Bit TimingSymbol t SYNC CAN SERIAL COMMUNICATIONS CONTROLLERFigure 7-5. A Bit Time as Implemented in the CAN Controller Table 7-9. CAN Controller Bit Time SegmentsTable 7-10. Bit Timing Relationships whereTable 7-10 defines the bit timing relationships of the CAN controller 87C196CB SUPPLEMENT 7.3.5.1 Bit Timing Equations7.4.1 Programming the CAN Control CANCON Register 7.4 CONFIGURING THE CAN CONTROLLERFigure 7-6. CAN Control CANCON Register Continued This bit globally enables and disables interrupts error, status-change, and87C196CB SUPPLEMENT Unchanged 7.4.2 Programming the Bit Timing 0 CANBTIME0 RegisterTSEG2 7.4.3 Programming the Bit Timing 1 CANBTIME1 Register87C196CB SUPPLEMENT Figure 7-8. CAN Bit Timing 1 CANBTIME1 RegisterComments 7.4.4 Programming a Message Acceptance FilterBit Time Requirement87C196CB 87C196CB SUPPLEMENTFigure 7-9. CAN Standard Global Mask CANSGMSK Register CANSGMSK87C196CB CAN SERIAL COMMUNICATIONS CONTROLLERFigure 7-10. CAN Extended Global Mask CANEGMSK Register CANEGMSKFigure 7-11. CAN Message 15 Mask CANMSK15 Register 7.5 CONFIGURING MESSAGE OBJECTS87C196CB SUPPLEMENT 7.5.1 Specifying a Message Object’s Configuration Figure 7-13. CAN Message Object x Identifier CANMSGxID0-3 Register 7.5.2 Programming the Message Object Identifier87C196CB SUPPLEMENT Access Type 7.5.3 Programming the Message Object Control Registers7.5.4 Programming the Message Object Data Program the CAN message object x control 0 CANMSGxCON0 register to indicate whether the message object is ready to transmit and to control whether a successful transmission or reception generates an interrupt. The least-significant bit-pair indicates whether an interrupt is pending 87C196CB SUPPLEMENTFigure 7-14. CAN Message Object x Control 0 CANMSGxCON0 Register CAN SERIAL COMMUNICATIONS CONTROLLER Figure 7-15. CAN Message Object x Control 1 CANMSGxCON1 Register 87C196CB SUPPLEMENTCAN SERIAL COMMUNICATIONS CONTROLLER Function 87C196CB SUPPLEMENTFigure 7-16. CAN Message Object Data CANMSGxDATA0-7 Registers 7.6 ENABLING THE CAN INTERRUPTS 87C196CB 87C196CB SUPPLEMENTFigure 7-17. CAN Control CANCON Register Continued CANCON ContinuedWhen the SIE bit in the CAN control register is set, the CAN controller generates a successful reception RXOK interrupt request each time it receives a valid message, even if no message ob- ject accepts it. If you set both the SIE bit Figure 7-17 and an individual message object’s RXIE bit Figure 7-18, the CAN controller generates two interrupt requests each time a message object receives a message. The status change interrupt is useful during development to detect bus errors caused by noise or other hardware problems. However, you should disable this interrupt during normal operation in most applications. If the status change interrupt is enabled, each status change generates an interrupt request, placing an unnecessary burden on the CPU. To prevent re- dundant interrupt requests, enable the error interrupt sources with the EIE bit and enable the re- ceive and transmit interrupts in the individual message objects 7.7 DETERMINING THE CAN CONTROLLER’S INTERRUPT STATUS Figure 7-20. CAN Status CANSTAT Register CAN SERIAL COMMUNICATIONS CONTROLLERFigure 7-21. CAN Message Object x Control 0 CANMSGxCON0 Register 87C196CB SUPPLEMENTRegister Mnemonic 7.8 FLOW DIAGRAMSA2594-01 Process message contents87C196CB SUPPLEMENT Figure 7-22. Receiving a Message for Message Objects 1-14 - CPU FlowRestart Process CAN SERIAL COMMUNICATIONS CONTROLLERFigure 7-23. Receiving a Message for Message Object 15 - CPU Flow same identifer as this 87C196CB SUPPLEMENTFigure 7-24. Receiving a Message - CAN Controller Flow Received frame withFigure 7-25. Transmitting a Message - CPU Flow Power UpUpdate CAN SERIAL COMMUNICATIONS CONTROLLERwith same identifer as 87C196CB SUPPLEMENTFigure 7-26. Transmitting a Message - CAN Controller Flow Received remote frame7.9.3 Bus-off State 7.9.1 Hardware Reset7.9 DESIGN CONSIDERATIONS 7.9.2 Software InitializationThe CAN controller synchronizes itself to the CAN bus by waiting for 128 bus idle states 128 occurrences of 11 consecutive recessive bits before participating in bus activities. During this sequence, the CAN controller writes a bit 0 error code to the LEC20 bits of the status register each time it receives a recessive bit. Software can check the status register to determine whether the CAN bus is stuck in a dominant state. Once the CAN controller is resynchronized with the CAN bus, it clears the BUSOFF bit and starts transferring messages again Special Operating Modes Page Figure 8-1. Clock Circuitry CHAPTER SPECIAL OPERATING MODES8.1 CLOCK CIRCUITRY Page Interfacing with External Memory Page 9.2 BUS TIMING MODES 9.1 ADDRESS PINSCHAPTER 9 INTERFACING WITH EXTERNAL MEMORY T AVDV = 3t 87C196CB SUPPLEMENTFigure 9-1. Modes 0 and 3 Timings T RLDV = 1tINTERFACING WITH EXTERNAL MEMORY Figure 9-2. Chip Configuration 1 CCR1 Registerno direct access † = always enabledFunction Figure 9-2. Chip Configuration 1 CCR1 Register Continued87C196CB SUPPLEMENT CCR1 ContinuedProgramming the Nonvolatile Memory Page 10.1 SIGNATURE WORD AND PROGRAMMING VOLTAGES 10.2 MEMORY MAP FOR SLAVE PROGRAMMING MODECHAPTER 10 PROGRAMMING THE NONVOLATILE MEMORY Table 10-3. Auto Programming Memory Map 10.3 MEMORY MAP AND CIRCUIT FOR AUTO PROGRAMMING87C196CB SUPPLEMENT Table 10-2. Slave Programming Mode Memory Map 74HC14 10.4 MEMORY MAP FOR SERIAL PORT PROGRAMMINGPROGRAMMING THE NONVOLATILE MEMORY Figure 10-1. Auto Programming CircuitSerial Port Programming Mode 10.4.1 Selecting Bank 0 FF2000-FF7FFFH10.4.2 Selecting Bank 1 FF8000-FFFFFFH Signal Descriptions Page A.1 FUNCTIONAL GROUPINGS OF SIGNALS APPENDIX A SIGNAL DESCRIPTIONSView of component as 87C196CB SupplementFigure A-1. 87C196CB 84-pin PLCC Package xx87C196CBxx87C196CB A.2 SIGNAL DESCRIPTIONSSIGNAL DESCRIPTIONS Figure A-2. 87C196CB 100-pin QFP PackageTable A-2. Description of Columns of Table A-3 Table A-3. Signal Descriptions87C196CB Supplement read or write. AINC# is sampled after each location is programmed or dumped SIGNAL DESCRIPTIONSTable A-3. Signal Descriptions Continued 87C196CB Supplement Table A-3. Signal Descriptions ContinuedTable A-3. Signal Descriptions Continued SIGNAL DESCRIPTIONS87C196CB Supplement Table A-3. Signal Descriptions ContinuedTable A-3. Signal Descriptions Continued SIGNAL DESCRIPTIONSA-10 Table A-3. Signal Descriptions Continued87C196CB Supplement A-11 SIGNAL DESCRIPTIONSTable A-3. Signal Descriptions Continued A-12 Table A-3. Signal Descriptions Continued87C196CB Supplement A-13 SIGNAL DESCRIPTIONSTable A-3. Signal Descriptions Continued 87C196CB Supplement A.3 DEFAULT CONDITIONSTable A-3. Signal Descriptions Continued Table A-4. Definition of Status SymbolsA-15 SIGNAL DESCRIPTIONSTable A-5. 87C196CB Pin Status Continued Page Glossary Page GLOSSARY characteristic transfer function of an A/D convertertwo adjacent code transitions on the A/D converter channel-to-channel matching errorcode width earity errorsSee off-isolation conversion result. Differential nonlinearity is astarting address of an interrupt service routine The characteristic of an ideal A/D converter. An ideallinearity errors. Quantizing error is the only error are to be serviced by interrupt service routines thatlinearity errors See interrupt service routineSee differential nonlinearity and nonlinearity Embedded Microcontrollers databook to determine terminal-based characteristic from the correserviced by interrupt service routines that you OTPROM. Consult the Automotive Products orprioritized interrupt directly to the interrupt service routine whenSee PTS control block repeatability error transitions from different actual characteristics takenideal A/D converter quantizing errorsample delay Successive approximation register. A component ofthe A/D converter interrupt controller for processing by an interrupt service routinescaled to remove zero-offset error and full-scale characteristic of the A/D convertercharacteristic process quantizing error, zero-offset error, full-scaleerror, differential nonlinearity, and nonlinearity isolation, and VCC rejection errorsPage Index Page INDEX Index-2 87C196CB SUPPLEMENT